The repeatability and accuracy of test plays a critical role of ensuring optimal test throughput.  The demand for semiconductor test reliability increases with the requirements for device performance.

Testing high performance devices comes with many test challenges:

• Noise Sensitivity – Low signal-to-noise ratio can make it challenging to distinguish between the device's response and background noise, affecting measurement accuracy.
• Signal Integrity – Factors like impedance mismatches, parasitic capacitance, and inductance can significantly affect the device performance and the accuracy of test measurements.
• Precision, Accuracy, Linearity – Measurement accuracy required when testing at µV/µA levels

Solid contact technology provides a solution to many of these test challenges with the following benefits:

• Excellent performance from DC to +50 GHz
• Low and repeatable CRES during production test
• Ultra-low inductance

As AI, communications, EV and self-driving automobiles become more ubiquitous, demands on IC performance increase exponentially. To meet these requirements and maintain cost effectiveness many IC companies are using hybrid technologies, in chiplet form, co-packaged to preserve the density of monolithic solutions and ease system design. Traditionally, monolithic devices have been tested with a final test at package to weed out bad components. Many times, probe is used to catch failures and avoid wasting money on good packages assembled with bad parts. With the emergence of chiplets, there is an added pressure on probe to establish “known good die” prior to packaging to avoid wasting money on good packaging and good chiplets assembled with one bad chiplet. Elevate believes a new paradigm in probe test must emerge to handle the added requirements of probing chiplets and is leading the way with innovative solutions.

The paper will discuss the bandwidth requirements for workload data as well as the zero overhead datalogging volumes required for yield learning as we look at data flows for several mobile and HPC class devices. To understand the complexity needs we will look at some of the multi-physics simulations that are required for device, DUT board thermals as well as Signal integrity (SI). We close with a look at using UCIe standard phy’s for high data rate test access.

Characterization and validation of chiplets-based packages poses unique challenges. These include investigating corner cases like the process-voltage-temperature (PVT) in the validation as well as in the production environments (deployment in compute servers). The challenges are further exacerbated since the sockets used in the production environment are different from the ones used in the validation environment. The conventional approach to active thermal control using thermoelectric coolers (TECs) and heat exchangers do not provide sufficient coverage for thermoregulation in one or more zones of the package due to package topologies. Furthermore, It is extremely difficult to design and implement a cost-effective system that has multi-zone sensing and temperature-controlled feedback to control the temperature in each zone of the package. Most thermal control unit (TCU) deployments need compressed air to activate the thermal head interfacing with the socketed processor, a controller unit with a software interface and a chiller to support the heat exchanger, all of which require periodic maintenance and monitoring. As such deploying TCUs in the production and validation environments poses insurmountable challenges. We propose an alternate approach using a heat exchanger with isolated zones matching the disaggregation in the chiplets-based package and connected to one or more chillers. By studying the thermal performance of each zone, the heat exchanger design is optimized to keep the thermal gradients between the zones in the package to a minimum. An isothermal boundary condition is realized by setting temperature offsets in the chillers and monitoring its stability for the duration of characterization. With adequate provisioning of heat removal in the chillers, it was found that maintaining an isothermal boundary condition is indeed feasible. This approach was realized in designing a multizone cooling/heating lid which mounts in both validation and production environments. Furthermore, the manufacturing cost of such passive thermal lids is a fraction of the TCU with no additional hardware needed. Augmentation of such passive thermal lids include an enclosure to maintain positive air pressure with dry air circulating inside to prevent condensation when testing at cold temperatures below the dew point. A quasi-active thermal lid can be designed by adding either a Raspberry Pi or a similar low-cost compute device to access the chiller temperature via a serial port and control it as needed for various testing conditions in a graphical user interface. Ampere computing has successfully implemented this approach in partnership with ISC International.

The shrinking of semiconductor transistor gates has enabled increased functionality to be integrated into a single chip. Different IP blocks such as memory, PCIE, USB, SERDES, WiFi, and cellular data are all integrated into a single chip and all of these functions have different frequency ranges and have historically had different impedance requirements. Historically, when testing these types of products, a one size fits all approach has been taken for test hardware based on the most critical or challenging feature to be tested. For example, SERDES circuits may be designed for 100Ω differential impedance and DDR circuits may be designed for 85Ω differential impedance, and the socket will be designed for 100Ω differential impedance. In this paper, the authors will compare a one size fits all approach for socket impedance with a mixed impedance socket to see whether the difference in performance is significant and whether the additional design complexity is justified. A comparison of both simulation and VNA measurement data will be included. The product to be tested will include 40Ω single ended/ 80Ω differential impedance, 85Ω differential impedance and 100Ω differential impedance features. The paper will provide an overview of the test PCB, surrogate device, socket design, and simulation and measurements.

Electro-Mechanical Relays (EMRs) are one of the stickiest pieces of technology (>80 years since introduction) that is present in modern day Semiconductor Test and ATE circuit designs. This trailing edge technology results in sub-optimal performance in high-volume semiconductor electrical test production and ATE test and measurement circuits. Solid State Relays (SSRs) bring signal switching and ATE resource switching into the modern era. Solid State Optronics has developed a family of Single Form C-SPDT and Dual Form C-DPDT Solid State Relays with Break-Before-Make timing control to address the shortcomings of legacy Electro-Mechanical Relay devices as deployed in Semiconductor Test and ATE applications.

This paper to present real-world application of Vector Network Analyzer (VNA) to test hardware transmission line performance validation. NXP's Closed-Loop Hardware Design process necessitates design target compliance test for the different segment of the signal path transmission line. To cover mathematical aspect, instrument implementation to assess frequency domain, and time domain performance of the hardware. To cover current challenges associated with fine-pitch packages with IP-specific impedance specifications. To include examples of de-embedding techniques and unknown segment or tool extraction.