Typical contactor pins for semiconductor final test are specified to have a lifetime of about 200k cycles (might vary over increased temperature and current). Ideally the contactor pin lifetime would be as long as possible to in order to reduce the disruption of replacement. The large number of variables in the chip manufacturing process create challenges measuring pin lifetimes. An experiment was designed to perform a controlled evaluation of the pin lifetime of a commonly utilized spring-loaded contactor pin. This provided a fundamental study of the degradation mechanisms that lead to accelerated wear out, performance degradation prior to failure of the contactor pin. The experimental design will be described along with surprising information about how pins wear and the effect on contact resistance.

Necessity of new elastomer technology to improve by replacing random particles of conventional elastomer by MEMS particles for lower CRES, longer longevity and more.

Development and implementation of a force-controlled device contacting application for the final test engineering handler “talos”, which controls the travel of the contacting unit by a predefined contact force.

Most production test contactor solutions deployed today utilize some sort of spring probe technology that has been derived from some previous implementation in a test cell. Even though certain spring probe ‘standards’ have been adopted, they usually result in a degradation of performance in the test cell needed today. A clear example of this is the ‘widespread’ adoption of a spring probe of 5mm (or so) compressed test height. This is a spring probe standard based on a probe design from 20 years ago, originally designed for test handlers that are almost forgotten. What is needed today is a modern standard of spring probes: one family that targets high-speed and high-performance GHz applications, and the other family that is high-performance mechanically, yet very robust for modern digital and RF applications. The high-performance GHz family can compete electrically with elastomer-based solutions yet retain mechanical robustness that can endure extreme temperature test environments, as in automotive applications. The high-performance mechanical probe family has a very large probe compliance that allows testing of very large modules and strips while maintaining reliable electrical contact and having excellent RF response. True probe families have the added benefit of having flexibility to arrange signal/ground/power pins in any configuration to optimize signals while maintaining standard test kit hardware. Customer applications will be presented for both high-GHz and high-compliance solutions, and what benefits have been achieved.

The expansion of data has lead to dramatic changes in the way data is moved around the world. From AI processers, the speed at which data is being transferred has grown at a dramatic rate in order to support these chipsets. Some of the key components in this data transfer include SerDes system for moving data within data centers, which is the backbone for data movement. In order to support this, PTSL is developing the NuvoRF probe that can be used to characterize high speed data channels in PCBs with pitches nearly 1mm, where other analytic probes are not able to provide high enough bandwidth performance at those bandwidths due to being configured as GS probes where the impedance is not well controlled to the top. The NuvoRF probe can be used to characterize data channels on PCBs up to speeds of PCIe Gen 7 at 128 Gbps and 224 Gbps PAM4 SerDes signal lines due to the NuvoRF being configurable to a GSSG design with good impedance control to the tip, ensuring that the high speed data channels are operating up to the necessary bandwidth. PTSL will present data on the NuvoRF probe and illustrate how it can be used to provide high fidelity measurements of in PCB channels, characterizing the PCBs prior to attachment of the ASIC. Some of the data PTSL will present includes both S-parameters and TDR measurements to representative structures, showing that we can measure these channels with very high BW capabilities, ensuring that the PCB can support these data rates.

Effective back-drilling strategies for 200G+ PAM4 Designs Over the past few decades, technology has seen tremendous growth on the highspeed networking and RF frequencies. It seems not too distant when the frequencies were in lower MHz and we started to worry about the potential Signal Integrity issues arising due to transmission line losses and reflections. Nowadays as high-speed networking is moving to 200G+ PAM4 designs and even higher Nyquist frequencies, the transmission line losses due to reflections and impedance mismatches are getting more and more critical with a focus to further tune PCB transmission lines with tighter impedances, refined and tuned via/drill structures, better and improved materials, and specifically back-drill capabilities. Back-drills have served a critical feature in the past for reducing the losses coming out of the transmission lines due to removal of excessive stubs on the transmission lines. However, as the data rates goes higher and higher, question remain on the effectiveness of back-drills on highspeed networking designs. This paper discusses in detail the effects of back-drilling on High-speed transmission lines and the effectiveness for stub-drilling for higher frequencies on 200G+ PAM4 designs. Authors: Hameem Ur Rahman – R&D Altanova [Advantest] Quaid Joher Furniturewala – R&D Altanova [Advantest]

This paper to present test hardware Signal Integrity (SI) design for SOC with complex I/O transmission line requirements. NXP products with high speed I/O's of different format or type. Different data rate, impedance on a single package. The concept of one size fits-all I/O impedance is replaced by IP - specific transmission line parameters. Signal path design to cater for unique trace impedances for: Ethernet PCIE-85 Ohms Differential Impedance USB-90 Ohms Differential Impedance DDR-80 Ohms Differential Impedance, 40 Ohms Single Ended Other I/O 100 Ohms Differential Impedance, 50 Ohms Single Ended Modeling, simulation and validation methods to facilitate optimum performance. Multi-impedance implementation on test sockets. Layout and stack-up management on Final Test Loadboard.

Summary of Abstract (to be published in TestConX website): Optimization of high-speed interconnect interfaces into PCBs suffers from difficulties finding optimal performance over wide frequency bands in the presence of many variable PCB layout parameters. Ideally it would seem desirable to run a large number of simulations with different parameter sets and compare results. This is in direct conflict with typically long run times and high demand on computational resources when using 3D finite-element-analysis (FEA), thus making it largely impractical to perform many multiple optimizations for comparison purposes. Simulation platforms such as SPICE circuit modelers allow for very fast computation times in the seconds range and it was shown in last year’s presentation "Into the PCB at 90 – high GHz signal launches" that under careful examination of the problem it becomes possible to allow use of SPICE engines for interconnect simulations. Doing so then also enables use of so-called 'Monte Carlo analysis' that relies on repeated random sampling to obtain a large number of numerical results. With it one can define a range of parameters for many individual components in the same design and allow those to vary at will. Because of the very high computational speed it is then a simple matter to run multiple Monte Carlo analyses in short order and obtain a comprehensive graphical representation and comparison for very large numbers of parameter combinations. It will therefore be shown here how this approach can be used to identify a ‘most agreeable solution’ and its associated parameter selection for a particular design. While the process of setting up and running SPICE Monte Carlo simulations is relatively straightforward it must be kept in mind that the real work in using this technique lies in establishing and running 3D FEA sub-models that allow for 'reverse engineering' the actual 3D interconnect design. This process requires knowledge of which significant parasitic capacitance/inductance elements must be accounted for and how to extract the SPICE parameters from the 3D FEA simulations. Brief examples of such 3D models will thus be used to illustrate this aspect. In the same context correlation between SPICE and 3D FEA simulation results will be examined. Finally, pros and cons of the proposed approach will be discussed.

The world needs precision semiconductor parts in a variety of applications. The need for that precision will only accelerate as semiconductor content is placed in new applications. Thus, the balance between the benefit of precision trim at test and the cost of executing that trim is a never-ending optimization journey. Active laser trimmed parts can deliver very high precision, equivalent to 24+ bits when using a more common OTP/EEPROM based trim, with almost no die cost area and no digital content. Nothing is free and active laser trimming requires more development time and advanced skillsets to deliver an optimized solution into production. This paper presents a new active laser trim methodology that requires less development time and developer skillset to achieve the same electrical result as the baseline method. A key challenge with optimizing laser trim solutions is balancing the inverse relationship between the precision of the final result and the speed at achieving it. A very high precision trim will always be slower than a comparable lower precision trim due to how the active laser trimming process works. Every method to mitigate that relationship comes at the cost of making the trim optimization process more complicated. This paper breaks that consequence by adding a new control signal between the control system and the laser trimmer. A high precision trim can be made much faster without making it more complicated. Various existing active laser trim control methods will be shared to explain the current state of art and its limitations. That foundation will be used to show how the new methodology is better. Plots of the electrical results will be shown to highlight where execution time is saved and that the post-trim results are unchanged. In addition, data from a 10k unit pilot run will be shown to highlight the top-level execution time savings and the same unchanged post-trim results.

Parametric over-the-air (OTA) testing of antenna-in-package (AiP) modules presents several additional challenges to the semiconductor testing community due to the requirement of using a measurement antenna to parametrically test the AiP module. This has several implications starting with the ATE measurement instrumentation, which needs to support frequencies in the mmWave range. The DUT test fixture design also needs to support mmWave frequencies, and the DUT socket now needs to incorporate a measurement antenna, which can add a significant degree of complexity as compared to traditional RF sockets. In the last few years several papers/presentations have been published on this topic by members of the industry which present different approaches and solutions to these challenges. In this presentation we will concentrate on high volume production testing of AiP modules, and the challenge of creating a multi-site (8-sites) OTA change kit that can be readily integrated into a standard commercial handler without any hardware modifications required to the handler itself. This flexibility and ease of integration to existing available hardware is a critical requirement to make parametric OTA production testing lower cost and readily accessible within the OSAT business model. We will describe the OTA change kit implementation concept. We will discuss critical points such as the measurement antenna, pick and place and pusher implementation, and also the blind-mate waveguide interconnect that is required to transmit/receive the mmWave signal from the measurement antenna to the module under test and ATE measurement instrumentation. We will show the results of testing devices with the OTA change kit. Special emphasis will be on the achievable index time and unit per hour rate. For this evaluation we utilized a demonstration AiP module developed by Advantest. which will also be described in the presentation including some parametric OTA measurement results with this demonstration vehicle. Finally, we will discuss the challenges and our experiences of site-to-site isolation on a multi-site OTA change kit and how those challenges can be addressed. In this presentation we will concentrate on high volume production testing of AiP modules, and the challenge of creating a multi-site (8-sites) OTA change kit that can be readily integrated into a standard commercial handler without any hardware modifications required to the handler itself. This flexibility and ease of integration to existing available hardware is a critical requirement to make parametric OTA production testing lower cost and readily accessible within the OSAT business model. We will describe the OTA change kit implementation concept. We will discuss critical points such as the measurement antenna, pick and place and pusher implementation, and also the blind-mate waveguide interconnect that is required to transmit/receive the mmWave signal from the measurement antenna to the module under test and ATE measurement instrumentation. We will show the results of testing devices with the OTA change kit. Special emphasis will be on the achievable index time and unit per hour rate. For this evaluation we utilized a demonstration AiP module developed by Advantest. which will also be described in the presentation including some parametric OTA measurement results with this demonstration vehicle. Finally, we will discuss the challenges and our experiences of site-to-site isolation on a multi-site OTA change kit and how those challenges can be addressed.

Every RF, mixed-signal and digital system needs a timing and clock subsystem to synchronize the generation and transportation of data. Standalone oscillators are very basic building blocks in such systems. The industry has a wide range of frequencies starting from a few kHz up to hundreds of MHz range of oscillators and they also come in various package types, package dimensions and pin count. For robust functioning of the system and in order to meet timing requirements, the performance of the Oscillator is very critical. This requires extensive characterization of the part for some of the critical parameters like Jitter, Phase Noise, frequency stability, Power Consumption, Output Clock Characteristics, Aging, Solder Shift and Power-Up Transients. Not all parameters can be tested on the Production due to hardware & test time limitation. Therefore a bench testing is the only way to guarantee these parameters reported in datasheet. It also demands the need for statistical data due to large volume requirement and to ensure quality parts are released with no failures reported in field. To make the testing efficient a Multi Site Bench Test is required. Single Site Bench Test is in-efficient and expensive. Multisite testing improves on the following •Coverage of devices •Validation timeline •Cost and time saving in terms of instrumentation, bench and setup. In this paper we present to you a mother board + daughter card solution / platform that is used to characterize TIs BAW based Oscillators.

The growth of the semiconductor industry drives a growth in the demanded testing abilities of Automated Test Equipment (ATE). This rising demand for high-voltage testing has prompted the need for innovative ATE solutions. Sponsored by Texas Instruments (TI), our project presents a solution that integrates with the existing system at TI and addresses the high-voltage demand. Our objective is to develop a cost-effective high-voltage resource board for ATEs used in semiconductor testing. The prototype is designed to deliver up to 4 kV differential output while maintaining accuracy, efficiency, and exceptional DC power quality. We aim to improve the power quality by using filters to minimize output voltage ripple. This resource board must seamlessly integrate with existing ATE setups while adhering to the limitations imposed by the available signals, power resources, and size constraints. An onboard microcontroller is employed to precisely regulate the voltage and timing required for the Device Under Test (DUT) in accordance with the ATE. The resource board incorporates a DC/DC converter, filters for enhancing DC power quality, and a control feedback loop, collectively optimizing the accuracy of ATE control. This allows the test engineers to effectively control the high voltage on the resource board by varying the input. Additionally, the onboard control serves to establish a current limit as a safeguard against potential short circuits in the DUT. In this paper, we discuss the process of design and development of our high voltage ATE resource and we discuss the characterization of the prototype and the DC/DC chosen. The output voltage, output current, output voltage ripple, output voltage accuracy, efficiency, and temperature, are the parameters this project aims to optimize.