As demand for smaller pin sizes and finer pitches continues to challenge conventional socket materials, there is a pressing need for stronger/stiffer materials with improved dimensional stability and stable electrical properties. This presentation introduces DuPont- Vespel® SCS-5700, a newly developed high-performance polyimide composite for precise micro-machining in next-generation 5.5G/6G test sockets and wafer probe applications in the semiconductor and electronics industry. With flexural modulus greater than 10 GPa, this material offers excellent mechanical properties and stiffness which allows drilling holes as small as 50 microns in diameter and 60 microns apart, thereby enabling higher hole density. Its superior dimensional stability and low thermal expansion over a wide range of temperatures and humidity leads to improved pin alignment and test efficiency. Furthermore, Vespel® SCS-5700 is a cost-effective solution that eliminates the need for expensive secondary machining steps to clean up holes. Its remarkable combination of strength, durability, and stable electrical properties make it an ideal choice for various precision machining applications, including 5.5G/6G test sockets and wafer level probe heads.

The test sockets used in semiconductor inspection equipment are becoming increasingly miniaturized each year. Resin-based materials are commonly used as the base material, but these also require advanced precision machining capabilities. Mitsubishi Gas Chemical has developed its own polyimide resin material called "Therplim," which possesses unique characteristics such as high heat resistance and low water absorption. By using Therplim as the base resin and compounding it with special ceramics, we have developed a new material, "TZ3300," which specializes in fine machining. TZ3300 can be provided in base material sizes over 100mm square and can also achieve thin layers of 0.4mm or less with minimal warping, which is essential for fine processing. In terms of fine machining capabilities, TZ3300 is not only capable of drill machining at the 30μm level but also excels in laser machining at the 20μm level. Notably, in laser machining, it can maintain wall thicknesses as small as 6μm while effectively minimizing burrs and burns. Additionally, it possesses unique features such as low water absorption and high insulation, making it highly suitable for advanced applications. For future developments, to meet the demands of the evolving market, we are also in the process of developing low-dielectric grades (suitable for high-frequency applications with a dielectric constant of 2.66, with further reductions planned) and conductive grades (anti-static with a resistivity of 10^6). These grades also utilize Therplim as the base resin and employ our proprietary compounding technology, which allows us to add new characteristics while maintaining fine machinability and high heat resistance. Currently, we have also initiated the development of a low thermal expansion coefficient grade (aiming for a CTE of approximately 10ppm, as a ceramic substitute) to address a broad range of needs, particularly those centered around test socket applications.

For decades, traditional socket housings have been either CNC machined or plastic molded. The process was often multi-stepped, where either the housing block was CNC machined and each individual pin hole had to be mechanically drilled, or it was molded and then post-mechanically drilled as a secondary operation. We have developed a new technology where we are capable of 3D printing a socket housing with extremely accurate tolerancing, down to 10 microns using various materials. All holes are 3D printed together with the rest of the housing in a single operation. The lead time for socket housing production is reduced to just a few days, with no need for post-machining. 3D printed housings can accommodate pinhole diameters or shapes required for 0.2 mm pitch and “balls anywhere” patterns. Housings can be 3D printed out of a variety of different materials, which can support many different semiconductor tests, both in positive and negative temperature ranges, as well as a diverse range of applied force and humidity. Socket housings can also be fully sealed and can support capillary liquid cooling inside the housing itself in a closed loop.

Teradyne's sustainability strategy is a comprehensive approach aimed at enhancing productivity and reducing environmental impact across the semiconductor industry. This strategy focuses on the development and implementation of innovative solutions that enable device manufacturers to improve production yields, reduce material use, and lower energy consumption, ultimately leading to a significant reduction in CO2 emissions.

Key challenges include the importance of reducing the carbon footprint of semiconductor test. This includes sustainable operating modes including energy reduction, efficient operating states, improved system throughput and productivity. The need for higher-efficiency instruments and power infrastructure, as well as the scalability and flexibility of instrumentation to reduce power consumption offer critical improvements. Collaboration with industry consortiums and customer partnership and ensure alignment with sustainability and business goals.

Key initiatives include the integration of preventive and predictive maintenance features, which enhance system availability and maintenance practices. Additionally, Teradyne's products, such as the UF+ and ETS-800 platforms, are designed to replace older systems, resulting in substantial energy and floor space savings. In addition, real-time sensors and monitoring enable reliable actionable power management actions to be taken. These include powering up and down instruments, metering and profiling power consumption and applying machine learning models to improve efficiency in real time. Through these efforts, Teradyne is not only advancing the semiconductor industry's transition to a greener future but also setting a benchmark for sustainability in technology development. This paper will delve into the specific strategies, metrics, and outcomes of Teradyne's sustainability initiatives, highlighting the company's dedication to environmental stewardship and innovation.

We will share some challenges you and your load board supplier will face if you're in the HPC arena. Some of these include larger board and panel sizes, aspect ratios, flip drilling, via plating, drill wander, layer alignment, sweet spots, board thickness limitations, and image rotation and weave effects. As devices get larger, the need for more layers for signal routing is the primary driver. Those signal layers need adjacent ground planes, compounding the layer count problems. What about the power domains? More and more we are seeing upwards of five to eight separate power layers. More layers mean thicker boards, and that can lead to PWB equipment limitations. Equipment designed to support 6mm to 8mm in thickness may not support the current standard of 8mm to 10mm. And what about all that space needed on the surface for component mounting? I could go on, but you’ll have to come and hear for yourself.

Mr. Tom Bresnan is a Senior Account Manager & Technical Sales Engineer with R&D Altanova of South Plainfield, NJ, joining them in August 2003. His more than 30 years of printed circuit manufacturing experience includes positions in various Engineering, Management and Sales roles for some of the world’s largest manufacturers of complex printed circuit boards. He is a distinguished lifetime member of the IPC Technical Activities Executive Committee and has presented and published numerous technical articles for the PWB industry on MCM-L’s, PWB manufacturing, and advanced plating capabilities. He’s a father of four and grandfather of six, and he resides in Florida with his wife, Joanne.

As more highly integrated and complex Integrated Circuits (IC) are developed, the time to fully validate them has increased. Each IC in a given product family may share some basic functionality but different test hardware is required due to device specific functions and packaging. Single site validation solutions do not offer great enough throughput to keep up with the demand for reduced product development time. Demands for over temperature testing at greater extremes renders traditional forced-air systems infeasible. Therefore, there is a need for a flexible, multi-site, temperature-chamber based validation platform. This presentation will present a platform that is flexible to test the majority of parts in a family, supports multi-site testing, supports wider temperature range testing, and is able to characterize TI’s precision Digital-to-Analog Converters (DAC).

Data centers and highspeed networks are constantly evolving at a tremendous rate. The data rates have been doubling every other generation through increasing density, doubling data-rate on enabling bi-directional data transfers.

The high-performance compute specially AI, CPU and GPU applications are already riding the current ride of data transfers in the realm of 224Gb PAM4 with a Nyquist frequency of 56GHz. With upcoming generations, data rates as high as 448G PAM4 and PAM6 with Nyquist frequencies ranging between 87 – 120GHz are possible.

PCB launches and routing gets significantly challenging as these data rates. This paper deals with how to design boards with these ludicrous speeds, what are new technologies to consider and understand the inflection point of the PCB technology as it comes to launching signals in the circuit boards at these speeds