Sunday March 2, 2025
There will be breaks including refreshments to provide networking time for Tutorial attendees.
Please note: attendance at the tutorial will be limited. Please sign-up early to not miss out!
1:00 to 3:00 pm
David L. Saums
DS&A
Thermal interface materials are available from hundreds of vendors and in thousands of different part numbers, creating a challenging test, evaluation, and selection procedure. This tutorial is intended to address these facets with an organized approach.
A relatively small number of TIM types are either designed specifically for semiconductor test or are directly applicable. Learning more about TIMs will allow the test engineer to set requirements and select solutions for their specific application.
This tutorial will include the following topics:
- A categorization methodology for thermal interface materials (TIMs) that is standardized for the thermal materials industry, with a number of very recent TIM developments identified by type and category. Understanding how the major categories are identified – and specific performance characteristics and intended function – is important to creating a short selection menu for evaluation.
- Identification of specific functional areas within the broad TIM range, followed by separating out polymers, graphitic, and metallic materials. Certain categories of TIMs are not appropriate for common application types and for semiconductor test, having been designed to meet specific functional requirements.
- Description of very recent developments in graphene-enhanced TIM types, hybrid liquid metal formulations, metallic pastes and gallium-containing materials, and phase-change metal alloys that are either currently in late-stage development or which have been released to production.
- Testing methods and specific practices, especially for newly-developed TIM types that have specific constraints on both testing practices and applications, will follow. Gallium-containing TIMs, for example, must be considered for testing and for application requirements with an understanding of this corrosive metal and containment, to prevent damage to joining copper and aluminum surfaces and components.
- Testing methodologies including ASTM D 5470-17 for through-plane thermal conductivity and thermal resistance; in-plane lateral testing methods; three-omega liquid, gel, and paste testing equipment and methods; and transient (structure function) methods. The use of standardized testing per ASTM D 5470-17 yields most consistent, accurate, and repeatable measurements. Transient test and thermal test vehicles (TTVs) are designed to produce in-situ test results that are closely matched to a specific package type, surface characteristics, and other non-standard conditions. Understanding the differences and the sequence of testing procedures is therefore important.
- Description of the use of thermal test vehicles (TTVs) for in-situ TIM testing for TIM0, TIM1, and TIM2. TTVs are very useful for testing with increased die warpage and non-flat surfaces, which is an increasing challenge for TIMs for bare-die package.
3:00 pm
Networking Break
3:30 to 5:30 pm
This tutorial will be an across-the-board (pun intended) look at those Printed Circuit Boards under your socket. Our focus will be the attributes, materials and processes required to produce those test interface boards we know you’ve been dying to learn more about. We’ll attempt to bring the board shop to you, giving you a better understanding of what you and your vendors are up against.
We’ll explore a brief history of the PCB or PWB (Printed Circuit/Wiring Board) industry in general and specifically concerning the ATE industry. We’ll see how pitch, layer count, overall thickness, and hole diameter, to name but a few of the most critical attributes, will impact the manufacturing (and co$t) of today’s test interface boards. We’ll examine the many options currently available for materials and how those options may be shrinking, right along with device pitch.
We’ll then move on to explain, in detail, the PWB manufacturing process; from raw materials through finished product.
Last but certainly not least, we’ll discuss quality and performance characteristics you can demand of your supplier(s). Even with today’s boards becoming more crowded (with components) and pitch and pin counts driving attributes ever smaller, there are ways to verify and validate the quality of your interface boards with your suppliers. We’ll show you how, with samples of our data gathered over years of process development, characterization and verification.
5:30 p
Welcome Reception
If this is your twenty-forth time attending TestConX, only your first, or somewhere in-between you will feel welcomed at the opening reception by friends old and new.
6:30 p
Dinner
The first of many excellent meals awaits as you get to network with other industry professionals. This is a great time to catch up with old colleagues or start meeting new friends.
7:30 p
It’s not fun to be on a tester all day…
I can’t do it since it’s all tribal knowledge (or I didn’t learn any of this in college)…
Too much stress and pressure to catch up all the project delays before it gets to test…
Not rewarding enough on the technical front...
There is no future in test engineering. AI will do it all soon…
These are some of the many things we have heard over the past twenty years as test engineers in the semiconductor industry. Most companies and experienced managers seem to know this and are working to remedy these concerns. However, there continues to always be a shortage of good test and product engineers and engineering managers. I.e., engineers who are internally motivated and energized to be in test and product engineering seem harder to find with each passing day.
Why is this the case and what do we as a community need to do different to engage and retain highly motivated and high performing staff in these functions? Or will AI really be the test engineer of the future… full automation from silicon data to test code to pass fail results?
We will have an open discussion on this topic to attempt to get a better understanding of the issues.
Dale Ohmart
Test Technology GroupHailin Wang
ElevATE SemiconductorIra Burton
Boise State UniversityKen Lanier
TeradyneTyler Waite
Micron9:00 p
Adjourn
Program subject to change without notice.