This session focus on application of the latest technologies to the test connect industry. Currently the standard approach for interposer printed circuit board (PCB) design layout still uses manual routing and heavily relies on the layout engineers’ experience. Addressing this design challenge via Artificial Intelligence (AI) and Machine Learning (ML) to build a smart router are presented first. The new router is the first in the industry and implements neural networks and genetic algorithms to extract the routing patterns from existing designs by data training. Then the system learns, discovers, and optimizes the routing for new layouts automatically. The second presentation explores the option of using a generic mother board and application specific interposers for package test or probe cards enabling quick design, rapid turn, and lower cost solution.

The Market Session is a very popular feature at TestConX since it provides the market context and commercial viability (in terms of supply and demand) of the end applications, the required test technology, and test consumables. First the technical and market forces that are shaping the future of test and burn-in will be presented. Semiconductors had an exceptional year in 2017 but softened in 2018. How did socket and contactor suppliers fare? Who were the top suppliers? We’ll hear the results in the Marketplace Report. The second presentation will address the global vision on More than Moore by digging into details of packaging technologies via reverse engineering analysis and examples. This will be followed by an extended market overview including semiconductors, packaging and test and burn-in historical performances and future trends.

Printed Circuit Boards (PCB) are the workhorse that enables electronic products in general and the test industry in specific. The session starts with a presentation on the complexity of the varied specifications in burn-in board (BIB) design. It then proposes a solution of a single BiB that can cater to different configurations resulting in significant cost savings. The second presentation takes a big picture view of the PCB, socket, and device in terms of electrical performance for operation frequencies > 80 GHz. It will be shown that only an optimized PCB design will allow performance at these levels. PCB fabrication constraints and an introduction to alternatives to the high-density interconnect (HDI) processes will be presented next that compares power integrity, signal integrity, throughput and reliability. Lastly a discussion about an innovative pitch translation methodology that reduce PCB design complexity and fabrication by 50% will be presented.

Electrical interconnect is a fundamental requirement of test and it must perform reliably and consistently in a wide range of applications and environments. This requires continuous innovation in probe/contact technologies and testing methodologies to meet current and future industry requirements. This session will cover the latest innovations and some unique test methodologies for validating them. The need for characterization of the current carrying capacity (CCC) of wafer-level chip scale packaging (WLCSP) probe heads, beyond the existing industry standard ISMI methodology, will start the session. Then the newly advanced coaxial solutions for probes and sockets for high-speed test applications will be presented. The third presentation will discuss a new test methodology that has been developed to compare force, deflection and electrical resistance for different types of probe tips and probe materials. Lastly, an introduction of the basics of electromigration effect and a finite element model for analyzing the electromigration effect between probe tips and solder bumps along with a few methods to alleviate this electromigration will be presented.

As product and test performance increases, a significant push for higher performance is required from printed circuit board (PCB) materials. Suppliers seeking out new materials and processes to support changing requirements for signal integrity, power delivery, performance due to the demands of 5G, Artificial Intelligence, the Internet of Things, and more are presented first. The second presentation attacks the challenges of higher frequency applications via resin type, reinforcement of glass fabric, modification of glass fiber weave, copper roughness and copper foil treatment. Selecting material with the appropriate dielectric loss and optimizing the impedance between PCB layers is the approach is presented third to solve the needs of 5G. Lastly, an innovative co-axial via based solution that eliminates the need for adding extra vias for shielding and crosstalk prevention is presented along with a simulation in the PCB fabrication environment.