Sunday March 3, 2019

There will be breaks including refreshments to provide networking time for Tutorial attendees.

Please note: attendance at the tutorial will be limited. Please sign-up early to not miss out!

Noon to 6:00 pm

Tutorial

Red Mountain 3

Optional Tutorial

"Beyond Sort, Burn-In, and Class Testing: Post Silicon Validation Hardware Strategy"

Tutorial Multimedia

John Kelbert

Principal Engineer

Intel

Amy Xia

Staff Mechanical Engineer

Intel

Tong Wa Chao

Staff Mechanical Engineer

Intel

This tutorial will provide a deeper understanding of post-silicon validation goals with an emphasis on the hardware development strategies for boards, sockets, and thermal tools to meet the needs and challenges of post-silicon validation work.

Post-silicon validation's goal is to verify product functionality against the Engineering Design Specification and takes place between initial silicon power on (PO) and product launch in parallel with Burn-in and packaged silicon classification testing (Class Test).

More & Biography

Among the challenges that post-silicon validation faces are silicon configuration capability and a growing product portfolio. By design, Intel develops generalized silicon products to support a wide-range of possible use cases. Physical system configurations are driven by memory (types, speeds, size) and thousands of possible input-output (IO) options to meet the needs of original equipment manufacturers (OEMs) and original device manufacturers (ODMs). New and emerging markets such as Autonomous Driving, Artificial Intelligence, 5G, and Cloud are growing the product portfolio. Together, silicon configuration and new markets, the number of silicon products to validate has more than doubled in the last five years.

Not only are post-silicon validation hardware solution providers challenged with supporting more products, the hardware solutions have become more complex. Among these more diverse number of products are larger packages/higher ball count/tighter pitch (driven by higher levels of integration) and/or products with higher power density as a result of higher performance. Compounding the challenges of validators and hardware providers is the need to provide faster time to market (TTM) at lower development costs across a growing product portfolio.

An overview of how hardware strategies and platforms have evolved and adapted to meet these challenges of post-silicon validation will be presented. It will include three specific case studies: scaling power measurement and challenges of >340 A; scaling socketing solutions and challenges with >300 µm of warpage; and scaling thermal tools and challenges for >500 W products with -40 C temperature requirement.

John Kelbert is a Principal Engineer within Intel’s Infrastructure & Platform Solutions Group. He joined in 1993 as a system validation hardware engineer, quickly progressing up to validation platform System Architect. Throughout his career at Intel, John played an active role in the evolution of Intel's validation hardware strategy and solutions and is presently driving the development of key technologies for future validation solutions.

Amy Xia is a mechanical and thermal architect at Intel. She is responsible for leading the development of solutions and qualification of next generation technologies in the areas of Socket, Retention, and Thermal to enable Validation and Manufacturing of across all major market segments. After receiving her PhD degree in fluid dynamics, she has been with Intel for more than 12 years.

Tong Wa (Tony) Chao is a mechanical engineer at Intel since 2004. His main research and development interests have been focused on mechanical design and stress analysis for system validation hardware and electronics packaging.

6:30 p

Welcome Reception

If this is your twenty time attending TestConX, only your first, or somewhere in-between you will feel welcomed at the opening reception by friends old and new.

7:30 p

Dinner

The first of many excellent meals awaits as you get to network with other industry professionals. This is a great time to catch up with old colleagues or start meeting new friends.

8:30 p

Invited Speaker

Red Mountain Ballroom

Invited Speaker - Jan Vardaman

"The Future of Advanced Packaging: Challenges Ahead on the Advanced Program"

“The Future of Advanced Packaging: Challenges Ahead”

Jan Vardaman

TechSearch International, Inc.

Presentation Download

E. Jan Vardaman

President and Founder

TechSearch International, Inc.

"The Future of Advanced Packaging: Challenges Ahead on the Advanced Program"

E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer. She is a member of SEMI, SMTA, IMAPS, and MEPTEC. She received the IMAPS GBC Partnership award in 2012 and the Daniel C. Hughes, Jr. Memorial Award in 2018. She is an IMAPS Fellow. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.

The high cost of moving to the next semiconductor technology node is changing the role of packaging and assembly in the electronics industry. New packaging solutions are being adopted to achieve the economic advantages that were previously met with silicon scaling. These options include silicon interposers, fan-out wafer level packages, and system-in-package. Some high-performance options are considered homogeneous integration, where die are partitioned. Others are classified as heterogeneous integration, including solutions in which some die functions are fabricated on the latest nodes, combined with other die fabricated on older less expensive nodes and linked together in the package. Combinations of memory and logic in the same package are increasingly common. Challenges for packaging and assembly in this new era include chip package interaction (CPI) for devices fabricated with low-k and ultra-low-k (ULK) dielectrics. Substrate warpage remains an issue and the need for known good die is becoming increasingly important. Test considerations factor into package choices. This presentation discusses the packaging changes and some of the issues being faced.