![Image](https://www.testconx.org/premium/wp-content/uploads/2023Korea/TestConXKorea2024_band_1500x500.jpg)
Suwon, South Korea - October 28-29, 2024
LA VIE D'OR
141-39 Botong-ri Jeongnam-myeon Hwaseong-si
Suwon-si, Gyeonggi-do, South Korea
TEL 031.352.7150
TestConX, over the course of its twenty-five-year history, has established itself as the preeminent event for test consumables, test cell integration, and test operations. The program scope includes packaged semiconductor “final” test, burn-in, system level test, and beyond to encompass all practical aspects of electronics testing such as validation, advanced packaging testing, module test, and finished product test.
Please join us for our 2nd annual TestConX Korea! Don’t miss this opportunity to be part of TestConX as we connect a larger community of test professionals and to participate in this excellent event!
For companies interested in exhibiting or sponsoring please see opportunities below.
Monday Program
13:00
“첨단 반도체 패키지 기술 동향”
Abstract (English)
With the increasing utilization of artificial intelligence such as Chat GPT, the amount of data used in the system is increasing rapidly. Semiconductor technology to respond to this data usage has already reached its limit with the scale-down of the existing method of chip technology, and semiconductor package technology allows the system to meet the necessary requirements of the system, which increases the importance of semiconductor package technology.
Semiconductor package technology has been developed in consideration of high speed, improved heat dissipation, stacking , high reliability, miniaturization, low cost, and environmental improvement, and advanced semiconductor package technology is a technology that satisfies these technology trends, and wafer-level packages, stack packages, and system-in-packages are referred to as advanced semiconductor package technologies. In this course, I will explain the definition and technology trends of these advanced semiconductor packages.
초록 (Korean)
Chat GPT 등 인공지능의 활용이 늘어나면서 시스템에서 사용하는 data의 양은 급격하게 증가하고 있다. 이러한 data 사용량을 대응하기 위한 반도체 기술은 기존의 방식인 칩 기술의 스케일 다운으로는 이미 한계에 도달하였고, 반도체 패키지 기술을 통하여 시스템에서 필요한 요구사항을 만족시킬 수 있게 되었고, 이 때문에 반도체 패키지 기술의 중요성은 커지게 되었다.
반도체 패키지 기술은 고속화, 열방출 향상, 적층, 고신뢰성, 소형화, 저비용, 환경 개선 등을 고려하여 개발되어 왔고, 첨단 반도체 패키지 기술은 이러한 기술 트렌드를 잘 만족시키는 기술로서 웨이퍼 레벨 패키지, 적층 패키지, 시스템 인 패키지가 첨단 반도체 패키지 기술로 언급되고 있다. 본 과정에서는 이 기술들의 정의와 기술 트렌드에 대해서 설명하려 한다.
![Image](https://www.testconx.org/premium/wp-content/uploads/2023Korea/MinsukSuh.png)
Dr. Minsuk Suh received his bachelor’s, master’s and doctoral degrees of material science and engineering from KAIST. More than 20 years, he involved in the development and mass production of RDL, Flip chip, WLCSP and TSV including HBM at SK hynix. At now, he is the leader of R&D center in Camtek Korea. In 2020, based on over 20 years of experience in the package industry, he wrote a book, ‘Package and Test that adds value to Semiconductor’, for package engineers as well as engineers at equipment, materials, and students studying packages.
Tuesday Program
09:00
09:15
Abstract - Biography (English)
This keynote presents a pioneering approach in semiconductor testing, where Artificial Intelligence (AI), specifically Large Language Models (LLMs) like GPT-4, is integrated with the expertise of test engineers. This collaboration represents a significant advancement in innovation, efficiency, and problem-solving within the industry, leading to higher quality work product, faster time to market and enhanced productivity for engineers. We illustrate this approach through multiple case studies where the AI assists engineering with: Analyzing semiconductor related data, Developing multi-stack software code for a special engineering project, Analyzing test engineering images, Algorithm development, and a Multi-agent collaboration applied across a multi-discipline engineering team. Central to this effort is the use of GPT-4 Turbo and GPT-4o, which aids test engineers in code development, debugging, trouble shooting, and image and data analysis offering expert recommendations to improve quality, efficiency, productivity and project outcomes. This highlights the transformative potential of AI in refining testing methodologies and enhancing the role of test engineers as innovators. As semiconductor testing faces increasing complexities, the synergy between AI and human expertise emerges as a vital solution. This keynote aligns with the forward-looking vision of TestConX, urging the semiconductor community to embrace AI-human collaboration as a key driver of the future of test engineering.
Keith Schaub is a seasoned expert in the semiconductor test industry, currently serving as Vice President of Technology and Strategy at Advantest America, Inc. With a career spanning over three decades, Keith has been at the forefront of integrating AI into semiconductor testing, revolutionizing the industry. He holds multiple patents, has founded a startup, and authored key publications on RF and wireless communications. Keith is also the host of the popular Advantest Talks Semi podcast, where he shares insights and explores emerging trends in the semiconductor world. As a respected speaker and author, Keith is known for his strategic insights and innovative solutions in the semiconductor test industry.
![Keith](https://www.testconx.org/premium/wp-content/uploads/2023Korea/keith028.png)
10:15
10:45
Break & Networking
Enjoy time to meet with the presenters and network while refreshments are served.11:15
Abstract (English)
This is equipment that tests the electrical characteristics of the die by dicing the HBM device in a wafer state, loading each die, and then contacting the probe on the probe card.
Each die is mounted on a hot and cold chuck, and then each die is sequentially aligned using an ultra-precision alignment machine and Vision Align algorithm technology.
12:15
Lunch and EXPO
Enjoy the delicious hot buffet lunch and networking time. Then take the time to explore the TestConX EXPO. There will be many great exhibits to connect electronic test professionals to solutions. You will be certain to see something new or meet someone new. As attendees to TestConX know, there is always excellent food, drinks, and time for attendees to network with exhibitors! TestConX EXPO will open at 12:15 and will remain open throughout the afternoon until 18:00
13:15
14:00
14:30
Break & Networking
Enjoy time to meet with the presenters and network while refreshments are served.15:00
Abstract - Biography (English)
In our paper, we present state-of-the-art and novelty probe designs for battery cell and EV-connector contacting applications. The purpose of these test products is to establish a temporary interconnect with the battery or a connector on an inverter, for testing the unit (end of line test).
Amongst the tests, we will cover topics like charge/discharge, OCV, weld joint test, and electrochemical impedance spectroscopy. Aside from testing, we will also have a special focus on the topic of battery cell formation and probe/contact choice for this application.
The challenge is that the parts need to remain in the formation rack for a very long time (several years) and that the formation takes quite a bit of time as well. All that has an impact on tip wear and probe life. We’ll be demonstrating what kind of methods can be implemented to ensure the parts can be cleaned with “in situ” methods without the need to remove the parts from the rack.
Lastly, we’ll present some new unique challenges such as the need for extremely increased current rating. As this can negatively affect probe performance, interesting novelty concepts are presented to cool down the probe in a tester or formation rack.
Matthias Zapatka
Academic Title: Dipl.-Ing.(FH)
Certifications: CIS
Matthias is the co-founder of INGUN USA, the North American subsidiary of the INGUN group. He has over 16 years of experience in the field of PCBA test, using spring-contacts, probes, and test fixtures. Matthias’ academic background is in RF & Wireless technologies. He graduated with honors from Konstanz University of Applied Sciences in Germany in 2008. He is a regular speaker at industry-related events. Matthias is IPC certified as an “Interconnect Specialist”. He resides in the western part of the United States.
초록 (Korean)
디바이스 테스트는 웨이퍼/디바이스 레벨에서의 칩의 전기적 및 기능적 신뢰성을 결정하기 위한 중요한 프로세스이며 테스트 프로브는 DUT와 테스터 사이의 접촉 인터페이스 역할을 하며 DUT의 패드/범프에 접촉하여 테스트를 위한 연결을 형성합니다.
테스트를 하는 동안 테스트 프로브에 산화물/찌꺼기가 쌓여 전기 전도도에 영향을 미치고 과검문제가 발생하게 됩니다. 산화물 또는 오염물이 쌓이는 것을 최소화하도록 테스트 프로세스 중에 클리닝 절차를 구현하는 것이 높은 신뢰성을 보장하는 데 있어서 중요합니다.
클린 패드/클린 웨이퍼는 쿠션 구조와 특수한 클리닝 수지 소재로 프로브 팁의 변형 없이 효과적으로 프로브를 클리닝합니다.
Abstract (English)
With dramatic increases in package sizes, total pin counts, multi-site socket counts, and the importance of signal integrity, test socket quality is critical to ensure optimal test performance. Despite the essential role the test socket plays in the electrical and mechanical test stack-up, the industry has relied on pin-level specifications and limited generic socket system-level characterization for the socket design validation and selection.
This, along with inefficient socket problem-solving techniques that rely on visual inspection, limited I/O test data information, and exclusion of PWR/GND pin performance data, often leads to endless cycles of reduced utilization and throughput issues in production.
This paper discusses case studies where ModusTest KGS️ improved the socket validation and selection process, production productivity, and overall efficiency and cost in the manufacturing process.
Biography (English)
In-Pyo Lee has over 20 years of experience in the semiconductor testing field, specializing in the development of Test Interface Boards for both memory and non-memory semiconductors. Currently, he is responsible for the development of Test Interface Board technology at TSE.
He has developed many test solution interface boards with a focus on high-speed, low-power, high-temperature, and fine-pitch requirements. He aims to share the latest technological trends in PCBs, which are the core materials of Test Interface Boards, under the topic of "Space Transformer & Fine Pitch Solution."
전기 (Korean)
이인표는 20여 년간 반도체 테스트 분야에서 경력을 쌓아왔으며, 메모리 및 비메모리 반도체의 Test Interface Board 개발에 전문성을 가지고 있습니다.
현재 TSE에서 Test Interface Board 기술 개발을 담당하고 있습니다.
고속, 저전력, 고온, 미세 피치에 중점을 둔 다수의 테스트 솔루션 인터페이스 보드 개발 경험이 있으며, "Space Transformer & Fine Pitch Solution"에 관한 주제로 Test Interface Board의 핵심 자재인 PCB에 대한 기술 트렌드를 공유하고자 합니다.
17:00
Lucky Draw
Door prizes for randomly selected attendees
(Must be present to win / void where prohibited)