In our paper, we present state-of-the-art and novelty probe designs for battery cell and EV-connector contacting applications. The purpose of these test products is to establish a temporary interconnect with the battery or a connector on an inverter, for testing the unit (end of line test).

Amongst the tests, we will cover topics like charge/discharge, OCV, weld joint test, and electrochemical impedance spectroscopy. Aside from testing, we will also have a special focus on the topic of battery cell formation and probe/contact choice for this application.

The challenge is that the parts need to remain in the formation rack for a very long time (several years) and that the formation takes quite a bit of time as well. All that has an impact on tip wear and probe life. We’ll be demonstrating what kind of methods can be implemented to ensure the parts can be cleaned with “in situ” methods without the need to remove the parts from the rack.

Lastly, we’ll present some new unique challenges such as the need for extremely increased current rating. As this can negatively affect probe performance, interesting novelty concepts are presented to cool down the probe in a tester or formation rack.

Matthias Zapatka
Academic Title: Dipl.-Ing.(FH)
Certifications: CIS

Matthias is the co-founder of INGUN USA, the North American subsidiary of the INGUN group. He has over 16 years of experience in the field of PCBA test, using spring-contacts, probes, and test fixtures. Matthias’ academic background is in RF & Wireless technologies. He graduated with honors from Konstanz University of Applied Sciences in Germany in 2008. He is a regular speaker at industry-related events. Matthias is IPC certified as an “Interconnect Specialist”. He resides in the western part of the United States.

디바이스 테스트는 웨이퍼/디바이스 레벨에서의 칩의 전기적 및 기능적 신뢰성을 결정하기 위한 중요한 프로세스이며 테스트 프로브는 DUT와 테스터 사이의 접촉 인터페이스 역할을 하며 DUT의 패드/범프에 접촉하여 테스트를 위한 연결을 형성합니다.

테스트를 하는 동안 테스트 프로브에 산화물/찌꺼기가 쌓여 전기 전도도에 영향을 미치고 과검문제가 발생하게 됩니다. 산화물 또는 오염물이 쌓이는 것을 최소화하도록 테스트 프로세스 중에 클리닝 절차를 구현하는 것이 높은 신뢰성을 보장하는 데 있어서 중요합니다.

클린 패드/클린 웨이퍼는 쿠션 구조와 특수한 클리닝 수지 소재로 프로브 팁의 변형 없이 효과적으로 프로브를 클리닝합니다.

With dramatic increases in package sizes, total pin counts, multi-site socket counts, and the importance of signal integrity, test socket quality is critical to ensure optimal test performance. Despite the essential role the test socket plays in the electrical and mechanical test stack-up, the industry has relied on pin-level specifications and limited generic socket system-level characterization for the socket design validation and selection.

This, along with inefficient socket problem-solving techniques that rely on visual inspection, limited I/O test data information, and exclusion of PWR/GND pin performance data, often leads to endless cycles of reduced utilization and throughput issues in production.

This paper discusses case studies where ModusTest KGS️ improved the socket validation and selection process, production productivity, and overall efficiency and cost in the manufacturing process.

In-Pyo Lee has over 20 years of experience in the semiconductor testing field, specializing in the development of Test Interface Boards for both memory and non-memory semiconductors. Currently, he is responsible for the development of Test Interface Board technology at TSE.

He has developed many test solution interface boards with a focus on high-speed, low-power, high-temperature, and fine-pitch requirements. He aims to share the latest technological trends in PCBs, which are the core materials of Test Interface Boards, under the topic of "Space Transformer & Fine Pitch Solution."

이인표는 20여 년간 반도체 테스트 분야에서 경력을 쌓아왔으며, 메모리 및 비메모리 반도체의 Test Interface Board 개발에 전문성을 가지고 있습니다.

현재 TSE에서 Test Interface Board 기술 개발을 담당하고 있습니다.

고속, 저전력, 고온, 미세 피치에 중점을 둔 다수의 테스트 솔루션 인터페이스 보드 개발 경험이 있으며, "Space Transformer & Fine Pitch Solution"에 관한 주제로 Test Interface Board의 핵심 자재인 PCB에 대한 기술 트렌드를 공유하고자 합니다.