In order to accurately predict the performance of the electronic devices before they are built,very careful electrical simulation is required. As data transfer rates of electronic devices increase, greater are the challenges to accurately simulate the electrical performance of the device under test (DUT). It is essential to very closely correlate the actual measured electrical data with the simulation results to improve overall accuracy. What impedance control means and the importance of a controlled impedance system for accurately obtaining test results of the DUT will be covered first. And the second presenter will discuss 3D electro-magnetic (EM) field simulation tools and how to accurately correlate simulation results to the actual measured data.

Poster Sessions are a great way to network through interaction with the poster presenters and other curious bystanders. At the same time enjoy the break refeshments and networking.

A dynamic panel session between suppliers and integrated device manufacturers (IDMs) on standardization methodology to define life cycle of socket technologies. Six panelists who are experts in their field will address this important topic moderated by two industry veterans. The audience can expect a classic debate between the supplier and IDMs regarding what life cycle really means, why there is so much variation and interpretation, what factors impact test methodology, and what ultimately contributes to the results from both perspectives. Bring your tough questions since audience participation is highly encouraged!

Debug and validation both at the die-level and system-level insure that the system or end-product is designed within specification and will work as intended without any issues even in the presence of manufacturing variations. There are significant challenges in both bare die qualification and new product validation to make sure that the final product is free of any “bugs” before shipping it to the end customer. Innovative debug and validation methods and techniques will show how many of these challenges may be solved. At the bare-die level and system level, these methods presented include: how to reduce time for first silicon bring-up and volume validation, how to qualify bare die using both thermal simulations and actual hardware testing, how to use single-node systems to scale out validation and mimic the customer data center environment, and how to effectively debug low power system on a chip (SOC) devices.