Spring-loaded test probes for in-circuit or functional test on printed circuit board assemblies have been around for many decades. However, for modern applications, a traditional three-piece “plunger-spring-barrel” design may just not be adequate to perform the test. Many of the modern test probes are much more complex than those from the early days, and the application range is much broader. Some probes consist of up to thirty and sometimes even more individual components. In this presentation, we first look at the history of probes and the basic design. We then take the audience on a journey how the designs have evolved and how to use these parts for a variety of tasks, which includes “conventional” circuit board test but also wire harness test, RF&Wireless test on test points as well as connectors, battery test on cell, module and pack level and even quantum computing applications. However, even the most sophisticated probe cannot be used “standalone” to perform a test; it needs a jig or a fixture to hold the parts in place. Therefore, we also look at state-of-the art modular test fixture designs and how the parts are integrated in there. While many engineers who regularly attend TestConX maybe familiar with “smaller” form factor probes (such as those used for socket test), this presentation gives an interesting insight in test solutions for those “larger” DUTs. Whereas most presentations at TestConX were for solutions of 0.35 mm pitch and below, we take it in the opposite direction and present technologies with spacings up to several centimeters (for example for battery or high-current test). We conclude the presentation with an outlook on “what’s next” on the horizon for test probe technologies.

Observations during contact testing show changes in properties such as current carrying capability after high current loading and/or mechanical actuation. Data from 110 device characterization measurements as well as a number of specific tests with different contact types will be presented. Findings should assist in contact selections and field application.

The Current Carrying Capacity (CCC) is a critical performance parameter for electric contacts, including spring probes used in test sockets. With the increasing thermal power of IC chips, there is growing interest in the CCC of contact probes. However, accurately measuring the CCC of spring probes and other contacts in real-world conditions presents significant challenges. Several factors can significantly impact CCC data measurements, such as:

• Steady vs. pulse currents
• Probes in still air vs. air with a specific flow rate
• Probes with or without socket material surrounding them

This paper will present heat transfer fundamental of current going through contacts, CCC measurements under various conditions, including both steady and pulse currents. Given the complexities involved in testing CCC under different factors, thermal simulations were employed to calculate the CCC of probes in diverse setups. The results from both measurements and simulations align closely, demonstrating the feasibility of using thermal simulation methods to predict the CCC of spring probes and other contacts across different operating environments. The paper provides detailed insights into the underlying thermal transfer principles, as well as the testing and simulation results.

This presentation presents a review of the developments of CO2 spray technology and how these improvements and enable new substrate cleaning options.

The rapid advancement of artificial intelligence (AI) has led to a surge in AI accelerators, which require high power, high bandwidth, and a complex software stack, posing unique quality requirements and test challenges. Reducing the cost of tests translates into lowering the overall cost of quality throughout the AI accelerator silicon lifecycle. This work aims to decompose conventional test challenges into four areas with limited interdependencies: (1) test coverage challenges, (2) interface challenges, (3) test setup challenges, and (4) usability challenges. High test coverage is achieved through a combination of parametric tests and logic tests. The interface to the Device Under Test (DUT) must be meticulously designed to ensure excellent signal integrity and power integrity, delivering high digital bandwidth and higher power to the DUT. Thermal observability and controllability become crucial components in testing the high-current, high-power, and low-current AI accelerators. Finally, replicating the complex AI software stack on Automated Test Equipment (ATE) is essential for improving usability, leading to higher engineering efficiency. This work will explore these areas with detailed examples.

This presentation details the development and implementation of an alternative sensor system for the final test engineering handler "talos". It was developed due to the challenges of detecting WLCSP (Wafer Level Chip Scale Packages) components with conventional laser sensors because of their reflective surfaces.

Heterogeneous package along with Chiplet has given the flexibility to integrate devices of various process nodes to build SOC for Hi-Performance-Compute (HPC) and Artificial Intelligence (AI) markets with best Time-To-Market (TTM) advantages.

With Chiplets the compute performance needs can be tailored for an optimized performance for a required end use application.

While the fundamental need for Heterogeneous Package is the Known-Good-Die (KGD) of Chiplets and associated chips like Power-Management-IC (PIMIC), to ensure the Final Test Yield It is essential to understand difference between Monolithic and Chiplets based integration to achieve the final product yield and hence the Cost.

This presentation will cover the Test challenges in detail.

ABSTRACT:

As functionality, speed, and performance continues to increase in semiconductor devices, semiconductor testing has become significantly more sensitive to electrical attributes of the test collaterals – sockets and boards.

The advances in simulation and metrology for test hardware design and measurement have been well documented throughout the history of BiTS and TestConX. More and more, taking a holistic approach to simulation in which the complete hardware solution is modeled – board and socket, is believed to provide the best opportunity to achieve first time right hardware performance.

In this paper, the authors will show a case study where only modeling a portion of the test hardware was not able to predict the real-world performance of the system resulting in an adverse impact performance at test.

The authors will share details about the product attributes, the gaps in the simulation process that did not identify the issue, how the problem manifested, and how it was resolved. The data on the initial hardware performance showing how the issue manifests, and the data after implementation of the solution will be share. Recommendations for how to improve the design process in the future will be proposed for discussion among conference participants.

This paper to present test hardware design of current generation of low voltage and high- performance SOC and or MCM. Devices at 0.76V VDD and lower presents challenges with it being so close to the noise floor.

Small pitch packages presents geometrical challenges when translated transmission line performance, RF parameters of the hardware. That is for high speed Serdes, analog 5G baseband and WIFI devices.

Compliance to PDN standard on power delivery is a major challenge. Power delivery in DC and frequency domain are with very tight margins for board, test sockets, connectors and power filter design. This paper to present solutions, mitigations, and new challenges to existing standards, practices on hardware design and socket parameter-specifications. Will broach advantages of new generation ATEs to these new test challenges.

Grounding is a fundamental aspect of RF system design, affecting signal integrity, noise reduction, and overall system stability. Different grounding strategies can lead to variations in impedance and signal loss. Our research investigates various grounding configurations and their impact on key performance metrics such as signal-to-noise ratio (SNR), transmission range, and data throughput. We conducted a series of simulations to evaluate the effects of grounding locations in different RF configurations. The results reveal significant differences in RF performance based on grounding strategies, with certain configurations offering substantial improvements in specific scenarios. In this presentation, we will discuss:

• Theoretical background on grounding and its role in RF systems.
• Simulation setup and methodologies used to assess RF performance
• Comparative analysis of various grounding locations and their impact on performance metrics.
• Case studies highlighting successful implementations
• Recommendations for optimizing grounding practices in diverse RF applications.

By understanding the interplay between grounding locations and RF performance, professionals in the field can make more informed decisions to improve the efficiency and reliability of their communication systems. Join us as we explore the critical aspects of grounding and unveil strategies for achieving superior RF performance.

High frequency performance is becoming more of an issue as data speeds have increased. This has created a corresponding increase in PCB microwave and millimeter wave performance requirements. This increase in required PCB performance speed makes VNA measurements of PCBs more critical. These measurements also require connectors or probes and cables for the connection of the PCB to the VNA. One such requirement is the need to test BGA feedback loops for 224 Gbps PAM4 data rates with a Nyquist frequency of 56 GHz. This PCB level testing can be done using a VNA to make insertion loss measurements through 56 GHz. The process of making these measurements on a PCB is shown in this paper.

The industry is moving to 224 Gbps high speed SERDES for leading network applications. The jump from 112 Gbps to 224 Gbps pose some major hurdles that must be overcome in order to properly test devices. The standard way of doing things will break if we don’t change our strategies.

We will present the challenges and discuss different strategies that can be implemented in order to achieve 224 Gbps performance and compare them against customer requirements. We will layout the limits of what we can achieve using each strategy with each and set realistic performance goals.

We also must expand the scope of our discussion to include sockets, loop back circuits, and testing methodologies in order to provide a complete solution.