With the rise of the RF sampling ADC/DAC, PCIe 5/6, 1.6/3.2T Ethernet, and other products with high-speed interfaces, how to effectively test these products has become a new hot issue. As these DUTs have the characteristics of both high-frequency and high-speed, it is worthwhile to explore how to better characterize their performance and reliability in real-world applications. On the other hand, testers themselves are facing the opportunity to completely update their architectures by adopting, for example, RF digitization, which allows them to gain enhanced or even completely new test capabilities by taking advantage of RF/high-speed digital hybrid technologies. This paper attempts to discuss these issues and to share with you some of the latest advances in this domain from MET.

In our paper, we present state-of-the-art and novel probe designs for battery cell and EV-connector contacting applications. The purpose of these test products is to establish a temporary interconnect with the battery or a connector on an inverter for testing the unit (end of line test). Among the tests, we will cover topics such as charge/discharge, OCV, weld joint test, and electrochemical impedance spectroscopy. Besides testing, we will also focus on the topic of battery cell formation and probe/contact choice for this application. The challenge is that the parts need to remain in the formation rack for a very long time (several years), and the formation process takes quite a bit of time as well. This has an impact on tip wear and probe life. We’ll demonstrate methods that can be implemented to ensure the parts can be cleaned with “in situ” methods without the need to remove them from the rack. Lastly, we’ll present some new unique challenges, such as the need for an extremely increased current rating. Since this can negatively affect probe performance, interesting novel concepts are presented to cool down the probe in a tester or formation rack.

This presentation discusses the challenges of automated test equipment (ATE) for testing battery management systems (BMS) in electric vehicles (EV) and introduces novel system-architectural solutions based on highly integrated system-on-a-chip (SOC) parametric measurement units (PMUs).

BMS measure temperature, voltage, and current in the battery-pack and balance battery cell charge. However, ATE for testing BMS in EVs has several challenges: Since a BMS device-under-test (DUT) may support a battery module with a series-connected stack of 16 or more Lithium-Ion cells, traditional ATE based on discrete devices has low density since it requires a high number of voltage and/or current source stimuli to emulate individual cell outputs. Second, since the DUT needs to be tested to microVolt (uV) and microAmpere (uA) accuracy, the ATE needs low-noise, precision voltage, and current sources which increase implementation complexity, size, and cost of discrete solutions. Moreover, the test stimuli to the BMS-DUT may require 100’s of Volts common-mode voltage relative to the channel differential voltage. Finally, since discrete-device-based ATE is not readily scalable, testing various BMS and battery-module configurations requires custom designs which take longer to build.

As a solution to the above challenges, this work first presents a series-connected stack of floating-ground PMUs which connect to the DUT and test if its cell-voltage (CV) and cell-balance (CB) terminal characteristics meet their specifications. The floating-ground-based topology meets both the high common-mode and the uV/uA precision requirements noted above. Each PMU has an isolated power supply for galvanic isolation from the system input power supply. In this configuration, digital-to-analog converters (DACs) integrated in each PMU drive the DUT CV and CB terminals in force-voltage (FV) or force-current (FI) mode and validate the DUT battery-cell measurement, input-current, and CB switch-transistor on-resistance capabilities from the DUT measure-current (MI) and measure-voltage (MV) responses. Each PMU FV or FI stimulus can be independently programmed by ATE software, thereby enabling test coverage of any battery cell condition. Following the above discussion, a second topology is presented which extends the testable DUT voltage range up to its absolute maximum rating by connecting each PMU in series with a high-voltage common-mode (CM), efficient switching-mode-power-supply (SMPS). The system is reconfigurable between the first high-precision and the second extended-voltage-range topologies using switching matrices. These switching matrices may be discrete to support more flexibility or integrated with the PMU, e.g., as co-packaged Micro-Electromechanical Systems (MEMS) switches. At the circuit level, integrated clamps in the PMU limit the voltage and current across the DUT. Additionally, each PMU has alarm features which detect temperature, voltage, current, and force/sense Kelvin faults.

BMS future trends include support for higher-voltage battery-packs, higher precision, various pack topologies as well as several new functions including active management and active cell balance. The presented architecture is scalable and readily addresses these trends because of design choices such as the integrated PMU SOC, series-connected PMUs / stacking of PMUs on CM power supply, and reconfigurability between the two topologies via the MEMS switching-matrix.

Diagnosis Plan for ATE Production Test Board of Large-Scale Chip

As the integration of chips and ATE (Auto Test Equipment) test sites increases, the complexity of the test board also grows exponentially. The total components count on partial test boards has exceeded tens of thousands, which increases the difficulties in ATE debugging and mass production maintenance.

The flying probe test and simple electrical tests from manufacturers are no longer sufficient to find faults on the test board. Every TE (Test Engineer) will encounter the following three problems:

• Unable to confirm in advance whether the test board is available before chip back.
• Unable to quickly troubleshoot whether the problem is caused by the test board.
• Unable to quickly locate failed components when encountering test board problems.

This material provides a systematic solution that can quickly solve the above problems:

• Hardware: No need to change the LB design or add any additional devices; only a low-cost customized dummy device is needed. This solution can cover all the important components on the ATE test board. The solution involves a one-time investment but remains available throughout the chip life cycle.
• Software: A code library is provided to simplify development efforts and achieve a user-friendly interface. Additionally, the fault component reference number can be printed out through the datalog, making maintenance very convenient.
• Revenue: Generally, there are more than 15,000 mounted components on a test board for AP chips. This method allows us to test over 90% of these components and has helped identify many functionally defective parts through the diagnosis plan.

大规模芯片ATE量产测试板诊断方案

随着芯片的复杂度增加和ATE测试的同测数增加，ATE测试板的复杂度也会指数级增加，部分测试板上的器件总数已经超过数万个，导致ATE测试板前期的验收调试及后续的量产维护都非常困难，测试板厂商能提供的飞针测试及简单的电气测试已经不够；

当前的困难主要是以下三点：

• 芯片回片前无法确认测试板是否能正常使用
• 量产时遇到异常无法快速排查是不是硬件导致的问题
• 量产时遇到硬件问题无法快速定位失效器件，影响产出

本次材料从硬件/软件两个维度提供了一种系统性的解决方案，可以快速解决以上问题：

• 硬件：在不改变现有测试板设计，不增加复杂度的情况下，用少量成本定制一套PCB，覆盖测试板上所有重要器件的测试路径，只需一次性投入，整个产品生命周期内都可以使用
• 软件：将Code Library化，简化开发工作，实现友好的用户接口，同时可以通过Log打印出Fail器件位号，方便工厂维护；
• 使用效果：通常AP芯片的测试载板上器件数量会超过15000个，使用本方案后器件覆盖率可超过90%，我们通过本方案排查到了不少异常的器件