With the rise of the RF sampling ADC/DAC, PCIe 5/6, 1.6/3.2T Ethernet, and other products with high-speed interfaces, how to effectively test these products has become a new hot issue. As these DUTs have the characteristics of both high-frequency and high-speed, it is worthwhile to explore how to better characterize their performance and reliability in real-world applications. On the other hand, testers themselves are facing the opportunity to completely update their architectures by adopting, for example, RF digitization, which allows them to gain enhanced or even completely new test capabilities by taking advantage of RF/high-speed digital hybrid technologies. This paper attempts to discuss these issues and to share with you some of the latest advances in this domain from MET.

Daniel Xiao, PhD. Chairman of Suzhou MET Technology Co., Ltd. Graduated from Peking University with a major in Signal and Information Systems. He is the Chairman of Suzhou MET Technology Co., Ltd. He has long been dedicated to the design and development of a new generation of highly reliable RF sampling transceiver module, leading his team to achieve the productization of high anti-interference RF sampling transceiver technology comparable to heterodyne architecture indicators.

MET, the company he founded, is a technology innovation company committed to the research and development of testers for RF/microwave and high-speed interface chips/module. MET possesses original breakthroughs and deep accumulation in supporting fields such as digital RF transceiver modules, measurement algorithms and models, and industrial test software.

随着射频采样ADC/DAC、PCIe 5/6总线产品、1.6/3.2T以太网等具备高速接口的产品的兴起，如何对这些产品进行有效的测试也成为一个新的热点问题。这类被测件兼具高频器件和高速器件的特征，从何种角度可以更好地表征他们在真实应用场景下的性能和可靠性值得被认真探讨。另一方面，测试机本身也面临着利用诸如硅基射频数字化技术来全面更新自身架构的机遇，这使得测试机自身通过发挥射频/高速数字混合技术的优点而获得了更强的、甚至全新的测试能力。本文试图对上述问题进行抛砖引玉式地探讨，与诸位专家分享美星科技在这个领域的一些最新的进展。

肖如吾博士，苏州美星科技有限公司董事长。毕业于北京大学，专业为信号与信息系统。他长期致力于新一代高可靠性射频采样收发模块的设计与开发，带领团队实现了与外差架构指标相当的高抗扰性射频采样收发技术的产品化。

美星科技，他创办的公司，是一家致力于射频/微波和高速接口芯片/模块测试设备研发的科技创新公司。美星科技在数字射频收发模块、测量算法与模型、工业测试软件等支撑领域具备原创突破和深厚积累。

In our paper, we present state-of-the-art and novel probe designs for battery cell and EV-connector contacting applications. The purpose of these test products is to establish a temporary interconnect with the battery or a connector on an inverter for testing the unit (end of line test). Among the tests, we will cover topics such as charge/discharge, OCV, weld joint test, and electrochemical impedance spectroscopy. Besides testing, we will also focus on the topic of battery cell formation and probe/contact choice for this application. The challenge is that the parts need to remain in the formation rack for a very long time (several years), and the formation process takes quite a bit of time as well. This has an impact on tip wear and probe life. We’ll demonstrate methods that can be implemented to ensure the parts can be cleaned with “in situ” methods without the need to remove them from the rack. Lastly, we’ll present some new unique challenges, such as the need for an extremely increased current rating. Since this can negatively affect probe performance, interesting novel concepts are presented to cool down the probe in a tester or formation rack.

Matthias Zapatka is the co-founder of INGUN USA, the North American subsidiary of the INGUN group. He has over 16 years of experience in the field of PCBA testing, specializing in spring-contacts, probes, and test fixtures. Matthias’ academic background is in RF & Wireless technologies. He graduated with honors from Konstanz University of Applied Sciences in Germany in 2008. He is a regular speaker at industry-related events and is IPC certified as an “Interconnect Specialist.” Matthias resides in the western part of the United States.

Fred Li is Working in Ingun China, Battery unit member of Ingun group. More than 10 years experience in automation and precision manufacturing. Now focus on the battery and its related industries.

在我们的论文中，我们展示了用于电池单元和电动车连接器接触应用的最先进和新颖的探针设计。这些测试产品的目的是在电池或逆变器上的连接器上建立临时互连，以便对单元进行测试（生产线末端测试）。在测试中，我们将涉及充电/放电、开路电压（OCV）、焊接接头测试和电化学阻抗谱等主题。除了测试外，我们还将关注电池单元的成形以及该应用中的探针/接触选择。挑战在于这些部件需要在成形架上保持很长时间（数年），而成形过程也需要相当长的时间。这会影响探针的磨损和使用寿命。我们将演示可以实施的方法，以确保这些部件可以通过“原位”方法进行清洁，而无需将其从架子上取下。最后，我们将介绍一些新的独特挑战，例如对极高电流等级的需求。由于这可能对探针性能产生负面影响，我们提出了一些有趣的新颖概念，用于在测试器或成形架中冷却探针。

Matthias Zapatka 是INGUN USA的联合创始人，该公司是INGUN集团在北美的子公司。他在PCBA测试领域拥有超过16年的经验，专注于弹簧接触器、探针和测试夹具。Matthias的学术背景为射频与无线技术，他于2008年以优异的成绩毕业于德国康斯坦茨应用科技大学。他经常在行业相关活动中演讲，并且是IPC认证的“互连专家”。Matthias居住在美国西部。

Fred Li在INGUN中国工作，是INGUN集团电池单元的成员。他拥有超过10年的自动化和精密制造经验，目前专注于电池及其相关行业。

This presentation discusses the challenges of automated test equipment (ATE) for testing battery management systems (BMS) in electric vehicles (EV) and introduces novel system-architectural solutions based on highly integrated system-on-a-chip (SOC) parametric measurement units (PMUs).

BMS measure temperature, voltage, and current in the battery-pack and balance battery cell charge. However, ATE for testing BMS in EVs has several challenges: Since a BMS device-under-test (DUT) may support a battery module with a series-connected stack of 16 or more Lithium-Ion cells, traditional ATE based on discrete devices has low density since it requires a high number of voltage and/or current source stimuli to emulate individual cell outputs. Second, since the DUT needs to be tested to microVolt (uV) and microAmpere (uA) accuracy, the ATE needs low-noise, precision voltage, and current sources which increase implementation complexity, size, and cost of discrete solutions. Moreover, the test stimuli to the BMS-DUT may require 100’s of Volts common-mode voltage relative to the channel differential voltage. Finally, since discrete-device-based ATE is not readily scalable, testing various BMS and battery-module configurations requires custom designs which take longer to build.

As a solution to the above challenges, this work first presents a series-connected stack of floating-ground PMUs which connect to the DUT and test if its cell-voltage (CV) and cell-balance (CB) terminal characteristics meet their specifications. The floating-ground-based topology meets both the high common-mode and the uV/uA precision requirements noted above. Each PMU has an isolated power supply for galvanic isolation from the system input power supply. In this configuration, digital-to-analog converters (DACs) integrated in each PMU drive the DUT CV and CB terminals in force-voltage (FV) or force-current (FI) mode and validate the DUT battery-cell measurement, input-current, and CB switch-transistor on-resistance capabilities from the DUT measure-current (MI) and measure-voltage (MV) responses. Each PMU FV or FI stimulus can be independently programmed by ATE software, thereby enabling test coverage of any battery cell condition. Following the above discussion, a second topology is presented which extends the testable DUT voltage range up to its absolute maximum rating by connecting each PMU in series with a high-voltage common-mode (CM), efficient switching-mode-power-supply (SMPS). The system is reconfigurable between the first high-precision and the second extended-voltage-range topologies using switching matrices. These switching matrices may be discrete to support more flexibility or integrated with the PMU, e.g., as co-packaged Micro-Electromechanical Systems (MEMS) switches. At the circuit level, integrated clamps in the PMU limit the voltage and current across the DUT. Additionally, each PMU has alarm features which detect temperature, voltage, current, and force/sense Kelvin faults.

BMS future trends include support for higher-voltage battery-packs, higher precision, various pack topologies as well as several new functions including active management and active cell balance. The presented architecture is scalable and readily addresses these trends because of design choices such as the integrated PMU SOC, series-connected PMUs / stacking of PMUs on CM power supply, and reconfigurability between the two topologies via the MEMS switching-matrix.

Sandeep D’Souza is a Principal Engineer with ElevATE Semiconductor working on integrated circuit and system design for Automated Test Equipment (ATE) applications. He has 24 years’ experience in the semiconductor industry on ATE, Semiconductor Device Modeling, Analog, Mixed-Signal and RF IC design, and systems design for Ultrasonic Sensor, Haptics, Audio and Touch-Controller applications. Prior to ElevATE, he was with Qualcomm, Semtech (Jariet), Skyworks and Conexant. He has 8 publications and 40+ issued / pending patents. He received his Bachelor, Master and PhD degrees all in Electrical Engineering from IIT Bombay, Purdue University and UCLA respectively.

本演讲讨论了用于测试电动汽车 (EV) 中的电池管理系统 (BMS) 的自动测试设备 (ATE) 所面临的挑战，并介绍了基于高度集成的片上系统 (SOC) 参数测量单元 (PMU) 的新型系统架构解决方案。

BMS 测量电池组中的温度、电压和电流并平衡电池单元电量。然而，用于测试电动汽车中 BMS 的 ATE 面临多项挑战：由于 BMS 被测设备 (DUT) 可能支持具有 16 个或更多锂离子电池串联堆栈的电池模块，因此基于分立设备的传统 ATE 密度较低，因为它需要大量电压和/或电流源刺激来模拟单个电池输出。 其次，由于 DUT 需要以微伏 (µV) 和微安 (µA) 的精度进行测试，因此 ATE 需要低噪声、精密电压和电流源，这会增加分立解决方案的实施复杂性、尺寸和成本。此外，对 BMS-DUT 的测试刺激可能需要相对于通道差分电压的数百伏共模电压。最后，由于基于分立器件的 ATE 不易扩展，因此测试各种 BMS 和电池模块配置需要定制设计，而这需要更长的时间来构建。

作为上述挑战的解决方案，这项工作首先提出了一个串联的浮地 PMU 堆栈，它们连接到 DUT 并测试其电池电压 (CV) 和电池平衡 (CB) 端子特性是否符合其规格。基于浮地的拓扑结构既满足上述高共模要求，也满足 µV/µA 精度要求。每个 PMU 都有一个隔离电源，用于与系统输入电源进行电气隔离。 在这种配置中，每个 PMU 中集成的数模转换器 (DAC) 以驱动电压 (FV) 或驱动电流 (FI) 模式驱动 DUT CV 和 CB 端子，并根据 DUT 测量电流 (MI) 和测量电压 (MV) 响应验证 DUT 电池单元测量、输入电流和 CB 开关晶体管导通电阻能力。每个 PMU FV 或 FI 刺激都可以由 ATE 软件独立编程，从而实现对任何电池单元条件的测试覆盖。根据上述讨论，提出了第二种拓扑，通过将每个 PMU 与高压共模 (CM)、高效开关模式电源 (SMPS) 串联，将可测试的 DUT 电压范围扩展到其绝对最大额定值。该系统可以使用开关矩阵在第一种高精度拓扑和第二种扩展电压范围拓扑之间重新配置。 这些开关矩阵可以是离散的以支持更大的灵活性，也可以与 PMU 集成，例如作为共同封装的微机电系统 (MEMS) 开关。在电路级，PMU 中的集成夹具限制了 DUT 上的电压和电流。此外，每个 PMU 都具有报警功能，可检测温度、电压、电流和强制/感测开尔文故障。

BMS 的未来趋势包括支持更高电压的电池组、更高的精度、各种电池组拓扑以及包括主动管理和主动电池平衡在内的多项新功能。由于设计选择，例如集成的 PMU SOC、串联 PMU/CM 电源上的 PMU 堆叠以及通过 MEMS 开关矩阵在两种拓扑之间进行重新配置，所提出的架构是可扩展的并且可以轻松应对这些趋势.

Sandeep D’Souza 是 ElevATE Semiconductor 的首席工程师，致力于自动测试设备 (ATE) 应用的集成电路和系统设计。 他在半导体行业拥有 24 年从业经验，擅长 ATE、半导体器件建模、模拟、混合信号和 RF IC 设计，以及超声波传感器、触觉、音频和触摸控制器应用的系统设计。在加入 ElevATE 之前，他曾就职于 Qualcomm、Semtech (Jariet)、Skyworks 和 Conexant。他发表了 8 篇论文，拥有 40 多项已发布/待批专利。他分别在孟买印度理工学院、普渡大学和加州大学洛杉矶分校获得了电气工程学士、硕士和博士学位.

Diagnosis Plan for ATE Production Test Board of Large-Scale Chip

With increasing chip integration as well as ATE test sites, the complexity of test boards also increased exponentially, resulting in some of the test boards having more that tens of thousands of component counts. This increases the difficulties in the both debugging and maintaining the test boards

The flying probe test and simple electrical test from manufacturers are no longer sufficient to find the faults of test board. Three main challenges faced are as follows:

• Unable to confirm in advance whether the test board is operational before retest.
• Unable to quickly ascertain if the boards are abnormal during mass production.
• Unable to quickly locate failed components when encountering test board problems resulting in lower productivity.

This material provides a systematic solution which can solve the above problems quickly through:

• Hardware: Using one-time investment low-cost customized dummy devices that can be utilized throughout the product life-cycle to cover all important components on the ATE test boards without the need for LB design changes or additional devices.
• Software: Code Library is made to simplify development efforts and achieve a friendly user interface. At the same time, the fault component reference number can be printed out through the datalog which is very convenient towards maintenance.

Results: Generally, there are more than 15000 mounted components on test board for AP chip, this method of test can cover 90% of them, and can successfully identified many functionally defective parts through the diagnosis plan.

Jiang Lei, joined UNISOC Co., Ltd in 2014. He serves as a Senior Staff Test Engineer in the SEG (System Engineer Group). With over 10 years of experience in ATE hardware design and SOC/PMIC/RF debugging, he is highly experienced in the design and simulation of high-speed and RF signals. Additionally, he holds 8 patents related to ATE.

大规模芯片ATE量产测试板诊断方案

随着芯片的复杂度增加和ATE测试的同测数增加，ATE测试板的复杂度也会指数级增加，部分测试板上的器件总数已经超过数万个，导致ATE测试板前期的验收调试及后续的量产维护都非常困难，测试板厂商能提供的飞针测试及简单的电气测试已经不够；

当前的困难主要是以下三点：

• 芯片回片前无法确认测试板是否能正常使用
• 量产时遇到异常无法快速排查是不是硬件导致的问题
• 量产时遇到硬件问题无法快速定位失效器件，影响产出

本次材料从硬件/软件两个维度提供了一种系统性的解决方案，可以快速解决以上问题：

• 硬件：在不改变现有测试板设计，不增加复杂度的情况下，用少量成本定制一套PCB，覆盖测试板上所有重要器件的测试路径，只需一次性投入，整个产品生命周期内都可以使用
• 软件：将Code Library化，简化开发工作，实现友好的用户接口，同时可以通过Log打印出Fail器件位号，方便工厂维护；
• 使用效果：通常AP芯片的测试载板上器件数量会超过15000个，使用本方案后器件覆盖率可超过90%，我们通过本方案排查到了不少异常的器件

雷江，2014年加入紫光展锐有限公司，担任测试工程系统架构部高级主任测试工程师。他有超过10年的ATE硬件设计经验和SOC/PMIC/RF的调试经验，并在高速信号和射频信号的设计/仿真方面有丰富的项目经验积累。此外，他还拥有8个与ATE硬件相关的专利。