Current RF applications, especially for mmWave case, faced challenging the signal performance, PCB design, manufacturing capability and simulation accuracy.

For general non-mmWave RF design, usually routing signal trace on PCB surface layer for below advantage: a. avoids add via in signal path to get better performance; b. lower design Dk and lower propagation delay; c. wider line width and lower loss.

But to mmWave design, application case needs route mmWave signal trace in PCB inner layer with via for below requirement: a. fanout many (example: more than 10ea) concentrated RF signals, even signal pins surrounded by ground pins, make signals can’t fanout on surface layer; b. small device pitch(<=0.35mm) need substrate board to convert device pitch to 1mm or more. So, mmWave design need use substrate board/ PTH via in signal path, it will put forward higher requirements for hardware design.

This presentation introduces some hardware experience on 26~47GHz mmWave signal delivery structure with plated through hole (PTH), it will focus on PTH via and board stack-up structure, trace length balance, fabrication considering and simulation optimization. This presentation uses an substrate and PCB design as an example and introduce some general PCB design methods with PTH for mmWave design.

Lu Liang, graduated from Tongji university in 2017, received master’s degree in engineering, joined Teradyne (Shanghai) Co., Ltd. as a hardware engineer in the same year, and engaged in ATE hardware interface circuit design. Mainly focused on providing ATE hardware test solutions, hardware load board design and signal integrity simulation for customer’s RF devices, successfully designing test circuits for different types of RF devices such as UWB/WIFI7/mmWave and helping customers achieve mass production.

目前的RF应用面临着信号性能，PCB 设计与制造，和仿真精度的挑战，特别是毫米波应用。 对于一般非毫米波的射频应用，硬件设计上通常由于以下原因把RF 信号线走在PCB表层：a. 避免RF路径上的via以获得更好的性能; b. 更小的设计Dk以获得更低的传输时延; c. 线宽更宽，损耗更小。但是对于毫米波频段的RF设计，由于以下原因需要将信号经由via走在内层: a. 扇出多个集中在一起的RF信号，甚至信号引脚被GND 引脚包围导致不能在PCB 表层扇出; b. device pitch ≤0.35mm, 需要基板将pin pitch转到1mm或者更大以实现性能要求。所以， 毫米波芯片的硬件设计会需要在信号路径上使用基板或PTH via, 这将对硬件设计提出更高的要求。

本讲稿介绍一些关于在26~47GHz毫米波信号传输结构中使用基板+PTH的硬件设计实践。着重在PTH和电路板堆叠结构、走线长度优化、制造考量和仿真优化。以一个基板+PCB设计为例，介绍一些毫米波设计使用过孔的通用PCB设计方法。

梁鲁，2017年毕业于同济大学，获得工学硕士学位，同年作为硬件工程师加入泰瑞达（上海）有限公司，从事ATE 硬件接口电路设计至今 。主要专注于为客户RF device 提供ATE 硬件测试方案、硬件实现和信号完整性仿真，成功为UWB/WIFI7/mmWave 等不同类型RF device设计测试电路并帮助客户实现量产。

In high-speed digital PCB, differential pairs are widely used to suppress power noise. The working characteristics of differential mode and common mode can be described and observed in the form of mixed mode S parameters. Among them, for SDD parameter, optimizing the impedance matching can help reduce signal reflection and improve transmission quality. For SCC, SCD, and SDC parameters, theoretically, modal transformation can be suppressed by reducing the asymmetry of the transmission path. The asymmetry of the path may come from the environment of vias, wiring method, placement of serial components in path, inter-pair skew, length match position and tune length.

To explore how to optimize SCD and SDC parameters, a pair of 32Gbps differential loopback signals with RC components in series was selected and a series of simulation experiments are conducted. By changing the above variables, the influence of inter-pair skew and symmetry of differential pairs on transmission quality was studied, and the following conclusions and optimization ideas were obtained:

• 1. The different distribution of ground and power in the environment of PN vias can cause impedance asymmetry. The longer the asymmetric via length, the larger the PN skew. Optimizing the position of GND vias and reducing the length of the asymmetric vias can optimize SCD and SDC parameters.
• 2. The relative position of PN components in the path will affect wiring. Keeping the relative positions of PN vias at different areas in the pathway consistent can reduce the asymmetry of wiring.
• 3. As for wiring, loose coupling routing has wider linewidth and smaller attenuation in long-distance applications. However, in the case of small pitches, using tightly coupling routing can achieve more symmetrical fanout.
• 4. Instantly PN length matching can reduce the influence of inter-pair skew, but in tight coupling routing, it will also cause impedance mismatch of differential pairs. Appropriate position and tune length of length match can reduce impedance mismatch and reduce the impact on SDD parameter.

Howard Shang, from Teradyne, received a bachelor's degree from Shanghai Jiaotong University in 2020. After graduation, he began his career as a hardware design engineer at Teradyne (Shanghai). He has one year’ experience in loadboard design and two years’ experience in signal and power integrity simulation. In the past three years, he has successfully provided hardware solutions for various chips, such as application processors, artificial intelligence chip chips, high-performance computing chips, and so on.

在高速数字PCB中，差分对被广泛用于抑制电源噪声。差模和共模的工作特性可以用混合模S参数的形式来描述和观察。其中，对于SDD参数，优化阻抗匹配有助于减少信号反射，提高传输质量。对于SCC，SCD和SDC参数，理论上可以通过减少传输路径的不对称性来抑制模态转化。通路中的不对称性可能来源于孔的周围环境，走线方式，通路中串行元器件的摆放，差分对内错位，配等长的位置和蛇形线突起长度。

为探索如何优化SCD和SDC参数，实验选取了一对中间串联有RC器件的32Gbps 差分信号，并进行了一系列仿真对比。通过改变上述变量，研究了差分对内错位和对称性对信号传输质量的影响，得出以下结论和优化思路：

1. 在PN孔的周围环境中，地孔和电源孔分布的不同会造成信号孔的阻抗不对称。不对称孔越长，PN错位越大。优化地孔位置，减少不对称孔孔长可以优化SCD，SDC参数。
2. 通路中串联PN元件的相对位置会影响走线，使通路中不同区域PN孔相对位置保持一致可以减少走线的不对称性。

尚昊，来自泰瑞达(上海)，于2020年获得上海交通大学学士学位。毕业之后，作为一名硬件设计工程师在泰瑞达开启职业生涯。他有一年的loadboard设计经验和两年的信号与电源完整性仿真经验。过去3年，他曾成功为多种芯片提供了硬件解决方案，如应用处理器，人工智能芯片，高性能计算芯片等。

As one important ATE supplier, we will also face some testing challenges like the high parallelism，low cost control, test time and different types automotive devices from the semiconductor manufacturer based on the fixed configuration, which also inevitably bring with higher requests for test solution. As you know, test cost and test time are the key elements for semiconductor manufacturers. Therefore, for better performance we need to consider some special or innovative solutions on the load board in advance, that can help reduce cost and test time by matching with code optimization.

This paper will introduce the solutions from some real cases which have been successfully applied to the customers production projects and gotten a good performance. There will be showed the test principle, hardware connection, test code and test time comparison in the following provided solution.

Kaitao Liu, from Global ADC, senior engineer. Joined Advantest China in 2016, work scope included test solution design for automotive, DTV and sensor chips, test program development and consulting with the top semiconductor companies for a long time.

作为全球领先的半导体测试设备供应商，我们时长面临着诸多的挑战，像客户提出的在测试中拥有更高的并行度，针对低成本和测试时间的控制以及在固定的配置下满足多种类型芯片的测试方案，这也必然对测试解决方案提出了更高的要求。众所周知，测试成本和测试时间是半导体制造商关注的关键因素。因此，为了在量产中取得更好的性能，我们需要提前在负载板上考虑一些特殊的或创新的解决方案，这些解决方案可以通过与代码匹配优化来帮助降低成本和测试时间。

论文主要介绍一些来自于真实案例的解决方案，这些方案都已经量产并且取得了较好的性能。在以下的方案中我们会讨论测试原理，硬件连接，测试代码和测试时间的比较。

刘凯涛隶属于爱德万测试全球应用开发中心，高级工程师。2016年加入爱德万测试中国，主要负责汽车电子芯片，媒体类和传感器类芯片测试方案的设计，测试程序的开发以及相关的咨询工作，长期与行业顶尖的半导体公司进行项目的开发以及管理工作。