With the rapid development of the semiconductor industry, the volume of data generated during the mass production process has increased dramatically, providing a rich source of information for semiconductor testing. This paper proposes an analytical method based on Gubo OneData big data system to mine and analyze the vast amount of semiconductor testing data to discover potential correlations between different testing phases. By constructing advanced data mining algorithms, this study is able to identify key test items affecting the performance of semiconductor products and further evaluate the interrelationships among these test items. The results show that by optimizing the testing process and eliminating redundant or inefficient test items, production costs can be significantly reduced while ensuring product quality. This paper details the entire process of data collection, preprocessing, feature selection, model construction, and validation, and presents practical application cases, proving the effectiveness and feasibility of the method in actual production environments. Ultimately, this study provides a new cost optimization strategy for the semiconductor industry, which helps to promote technological progress and economic benefits in the industry.

Keywords: Semiconductor Testing; Big Data Analysis; Data Mining; Cost Optimization; Correlation Analysis

随着半导体行业的快速发展，大规模生产过程中产生的数据量急剧增加，为半导体测试提供了丰富的信息资源。本文提出了一种基于孤波OneData大数据系统的分析方法，旨在通过挖掘和分析海量半导体测试数据，发现不同测试阶段之间的潜在相关性。通过构建先进的数据挖掘算法，本研究能够识别出影响半导体产品性能的关键测试项目，并进一步评估这些测试项目之间的相互关系。研究结果表明，通过优化测试流程，剔除冗余或低效的测试项目，可以显著降低生产成本，同时保证产品质量。本论文详细介绍了数据收集、预处理、特征选择、模型构建和验证的全过程，并展示了实际应用案例，证明了该方法在实际生产环境中的有效性和可行性。最终，本研究为半导体行业提供了一种新的成本优化策略，有助于推动行业的技术进步和经济效益的提升。

关键词：半导体测试；大数据分析；数据挖掘；成本优化；相关性分析

According to the yole2023 report, the production value of silicon-based biomedical chips is expected to reach US$900 million by 2027. After the outbreak of COVID-19, many medical institutions found that traditional PCR testing was too slow. The need for fast detection led many companies to invest in the development of new types of BioMEMS. MEMS technology can reduce the size of BioMEMS chips and integrate microfluidic systems. The microstructure on BioMEMS can effectively reduce the usage of reagents. The testing requires only a small amount of sample, reagent, and testing time to obtain results. On the other hand, even with the strong performance of BioMEMS, due to the lack of mature mass production testing technologies, the low coverage rate of mass production testing causes the BioMEMS production capacity to be unable to increase.

This study developed a wet testing platform for BioMEMS chips and achieved stable and highly reproducible measurement results. BioMEMS chips require additional wet testing to verify product yield. In the wet testing process, the test solution is dispensed onto the sensing area of the chip test key, the Kelvin pin makes contact with the pad, and then electrical testing can commence. In addition, due to the restriction of the structure and size of the BioMEMS chip, the volume of the solution to be tested must be controlled within a micro volume of 1 μl. Based on the above situations, this study developed the wet testing platform according to the droplet testing method used in the past. The wet testing platform integrates and optimizes the probe station, semiconductor analyzer, and microfluidic control system. The testing method also verified the influencing factors such as solution concentration, different solutions, cleaning methods, testing time, and needle force, and used the experimental results to improve the testing process. Additionally, this study developed a water-retaining shield method for long-term testing. The shield prevents test sample evaporation and environmental effects. In long-term testing, the shield prolonged the testing time and stabilized the measurement data. This testing platform and process were also verified with the BioMEMS chips, and the measurement data of electrical properties not only showed accuracy but also reproducibility. In summary, the developed wet testing platform can provide reliable electrical measurement capability and has the potential to be developed into a semi-automatic and fully automatic testing platform. The technology is expected to be applied in the field of contract manufacturing testing in the future.

The compute power of stationary Small Form Factor (SFF) systems, such as desktops or Internet-of-Things (IOT) edge devices, are often thermally limited by the constrained space which makes it a challenge to support the Processor Base Power (also known as Thermal Design Power, i.e. TDP). While customers want to take full advantage of Intel processors with turbo performance, it is even more incredibly challenging to meet the additional thermal requirements by using traditional air-cooling technology in SFF systems. What adds to the pain point is that the system often operates in high operating ambient temperature (in the range of 50-60°C) for IOT applications.

Liquid immersion cooling is one of the most recent innovative technologies in which electronic systems are submerged in a non-conductive liquid bath to allow much more effective cooling. While it is commonly deployed for heat-intensive large-scale servers, we are taking proactive measures to perform sensitivity study to miniaturize immersion cooling to a desktop-tower-size system. The goal of this study is to achieve the smallest possible tower size with the targeted power dissipation. We will demonstrate the proof-of-concept (POC) system equipped with single phase liquid immersion cooling and measure the temperature on the dummy heater units, which mimic an Intel processor and a discrete graphic component. A series of parametric studies were performed to optimize the system in order to achieve the targeted power dissipation.

This paper presents the optimization approach and the components that were changed to arrive at the final POC. The POC that we present in this study measures 160mm (W) x 405mm (H) x 300mm (L) with volumetric size approximately 19.4L. The combined total power dissipation from the heaters is 650W. This POC is the smallest form factor that we can achieve based on the design requirements we have set forth. We believe this concept study with immersion liquid cooling can be scaled to Intel high performance processors with a discrete graphics card which brings the next level of user experience in the desktop, IOT, and workstation user space.

See, Khai Ern

Principal Engineer, Intel Client Computing Group

Khai Ern is currently the Platform Architect in the CCG-Malaysia Client Customer Engineering team at Intel. His experience spans multiple computing segments, from tablets and laptops to desktop PCs. He was part of the pioneering team that created the Intel Compute Stick and the first Intel Dual Screen Device Proof-of-Concept prototype, which eventually became successful customer products. His current focus is on defining the system architecture for the next generation of laptop systems, where he collaborates with PC industry players to advance the compute user experience. He is an active technical paper writer with over 30 publications and presentations at technical conferences, where he has received multiple best paper awards.

In the dynamic and competitive semiconductor industry, optimizing test equipment throughput and managing thermal performance are essential for efficiency and productivity. However, predicting automation throughput and thermal behavior remains a complex task. This presentation explores how simulation can transform the prediction of both automation throughput and thermal performance for semiconductor test equipment.

By using simulation, we can create virtual models that replicate real-world semiconductor testing conditions. This discussion will cover how simulation allows us to model the intricate interactions between equipment modules, processes, resources, and thermal dynamics, enabling accurate forecasts of both performance and thermal characteristics. We will also delve into the benefits of using simulation, such as optimizing equipment utilization and power loads. By modeling the automation process flow, potential bottlenecks and inefficiencies can be identified, allowing for proactive adjustments and continuous improvement.

This presentation will provide detailed examples of how thermal simulation can be leveraged to enhance the design of thermal solutions, effectively addressing challenging thermal issues in semiconductor testing. We will explore specific cases where thermal simulation has been used to identify and mitigate thermal challenges during testing, such as thermal hotspots and thermal gradients.

Key Takeaways:

• Understanding the role of simulation in predicting automation throughput and thermal performance for semiconductor test equipment.
• Examples of simulation optimizing equipment utilization and predicting thermal behavior of a DUT.
• Benefits of using simulation, including optimized resource utilization, reduced cycle times, improved equipment efficiency, and thermal load management.
• The role of simulation in scenario analysis and data-driven decision-making for continuous improvement.
• Strategies for leveraging simulation to drive efficiency and gain a competitive edge in the semiconductor industry.

With the rise of the RF sampling ADC/DAC, PCIe 5/6, 1.6/3.2T Ethernet, and other products with high-speed interfaces, how to effectively test these products has become a new hot issue. As these DUTs have the characteristics of both high-frequency and high-speed, it is worthwhile to explore how to better characterize their performance and reliability in real-world applications. On the other hand, testers themselves are facing the opportunity to completely update their architectures by adopting, for example, RF digitization, which allows them to gain enhanced or even completely new test capabilities by taking advantage of RF/high-speed digital hybrid technologies. This paper attempts to discuss these issues and to share with you some of the latest advances in this domain from MET.

In our paper, we present state-of-the-art and novel probe designs for battery cell and EV-connector contacting applications. The purpose of these test products is to establish a temporary interconnect with the battery or a connector on an inverter for testing the unit (end of line test). Among the tests, we will cover topics such as charge/discharge, OCV, weld joint test, and electrochemical impedance spectroscopy. Besides testing, we will also focus on the topic of battery cell formation and probe/contact choice for this application. The challenge is that the parts need to remain in the formation rack for a very long time (several years), and the formation process takes quite a bit of time as well. This has an impact on tip wear and probe life. We’ll demonstrate methods that can be implemented to ensure the parts can be cleaned with “in situ” methods without the need to remove them from the rack. Lastly, we’ll present some new unique challenges, such as the need for an extremely increased current rating. Since this can negatively affect probe performance, interesting novel concepts are presented to cool down the probe in a tester or formation rack.

Matthias Zapatka

Academic Title: Dipl.-Ing.(FH)

Certifications: CIS

Matthias is the co-founder of INGUN USA, the North American subsidiary of the INGUN group. He has over 16 years of experience in the field of PCBA testing, specializing in spring-contacts, probes, and test fixtures. Matthias’ academic background is in RF & Wireless technologies. He graduated with honors from Konstanz University of Applied Sciences in Germany in 2008. He is a regular speaker at industry-related events and is IPC certified as an “Interconnect Specialist.” Matthias resides in the western part of the United States.

This presentation discusses the challenges of automated test equipment (ATE) for testing battery management systems (BMS) in electric vehicles (EV) and introduces novel system-architectural solutions based on highly integrated system-on-a-chip (SOC) parametric measurement units (PMUs).

BMS measure temperature, voltage, and current in the battery-pack and balance battery cell charge. However, ATE for testing BMS in EVs has several challenges: Since a BMS device-under-test (DUT) may support a battery module with a series-connected stack of 16 or more Lithium-Ion cells, traditional ATE based on discrete devices has low density since it requires a high number of voltage and/or current source stimuli to emulate individual cell outputs. Second, since the DUT needs to be tested to microVolt (uV) and microAmpere (uA) accuracy, the ATE needs low-noise, precision voltage, and current sources which increase implementation complexity, size, and cost of discrete solutions. Moreover, the test stimuli to the BMS-DUT may require 100’s of Volts common-mode voltage relative to the channel differential voltage. Finally, since discrete-device-based ATE is not readily scalable, testing various BMS and battery-module configurations requires custom designs which take longer to build.

As a solution to the above challenges, this work first presents a series-connected stack of floating-ground PMUs which connect to the DUT and test if its cell-voltage (CV) and cell-balance (CB) terminal characteristics meet their specifications. The floating-ground-based topology meets both the high common-mode and the uV/uA precision requirements noted above. Each PMU has an isolated power supply for galvanic isolation from the system input power supply. In this configuration, digital-to-analog converters (DACs) integrated in each PMU drive the DUT CV and CB terminals in force-voltage (FV) or force-current (FI) mode and validate the DUT battery-cell measurement, input-current, and CB switch-transistor on-resistance capabilities from the DUT measure-current (MI) and measure-voltage (MV) responses. Each PMU FV or FI stimulus can be independently programmed by ATE software, thereby enabling test coverage of any battery cell condition. Following the above discussion, a second topology is presented which extends the testable DUT voltage range up to its absolute maximum rating by connecting each PMU in series with a high-voltage common-mode (CM), efficient switching-mode-power-supply (SMPS). The system is reconfigurable between the first high-precision and the second extended-voltage-range topologies using switching matrices. These switching matrices may be discrete to support more flexibility or integrated with the PMU, e.g., as co-packaged Micro-Electromechanical Systems (MEMS) switches. At the circuit level, integrated clamps in the PMU limit the voltage and current across the DUT. Additionally, each PMU has alarm features which detect temperature, voltage, current, and force/sense Kelvin faults.

BMS future trends include support for higher-voltage battery-packs, higher precision, various pack topologies as well as several new functions including active management and active cell balance. The presented architecture is scalable and readily addresses these trends because of design choices such as the integrated PMU SOC, series-connected PMUs / stacking of PMUs on CM power supply, and reconfigurability between the two topologies via the MEMS switching-matrix.

Diagnosis Plan for ATE Production Test Board of Large-Scale Chip

As the integration of chips and ATE (Auto Test Equipment) test sites increases, the complexity of the test board also grows exponentially. The total components count on partial test boards has exceeded tens of thousands, which increases the difficulties in ATE debugging and mass production maintenance.

The flying probe test and simple electrical tests from manufacturers are no longer sufficient to find faults on the test board. Every TE (Test Engineer) will encounter the following three problems:

• Unable to confirm in advance whether the test board is available before chip back.
• Unable to quickly troubleshoot whether the problem is caused by the test board.
• Unable to quickly locate failed components when encountering test board problems.

This material provides a systematic solution that can quickly solve the above problems:

• Hardware: No need to change the LB design or add any additional devices; only a low-cost customized dummy device is needed. This solution can cover all the important components on the ATE test board. The solution involves a one-time investment but remains available throughout the chip life cycle.
• Software: A code library is provided to simplify development efforts and achieve a user-friendly interface. Additionally, the fault component reference number can be printed out through the datalog, making maintenance very convenient.
• Revenue: Generally, there are more than 15,000 mounted components on a test board for AP chips. This method allows us to test over 90% of these components and has helped identify many functionally defective parts through the diagnosis plan.

Jiang Lei, joined UNISOC Co., Ltd in 2014. He serves as a Senior Staff Test Engineer in the SEG (System Engineer Group). With over 10 years of experience in ATE hardware design and SOC/PMIC/RF debugging, he is highly experienced in the design and simulation of high-speed and RF signals. Additionally, he holds 8 patents related to ATE.

大规模芯片ATE量产测试板诊断方案

随着芯片的复杂度增加和ATE测试的同测数增加，ATE测试板的复杂度也会指数级增加，部分测试板上的器件总数已经超过数万个，导致ATE测试板前期的验收调试及后续的量产维护都非常困难，测试板厂商能提供的飞针测试及简单的电气测试已经不够；

当前的困难主要是以下三点：

• 芯片回片前无法确认测试板是否能正常使用
• 量产时遇到异常无法快速排查是不是硬件导致的问题
• 量产时遇到硬件问题无法快速定位失效器件，影响产出

本次材料从硬件/软件两个维度提供了一种系统性的解决方案，可以快速解决以上问题：

• 硬件：在不改变现有测试板设计，不增加复杂度的情况下，用少量成本定制一套PCB，覆盖测试板上所有重要器件的测试路径，只需一次性投入，整个产品生命周期内都可以使用
• 软件：将Code Library化，简化开发工作，实现友好的用户接口，同时可以通过Log打印出Fail器件位号，方便工厂维护；
• 使用效果：通常AP芯片的测试载板上器件数量会超过15000个，使用本方案后器件覆盖率可超过90%，我们通过本方案排查到了不少异常的器件

雷江，2014年加入紫光展锐有限公司，担任测试工程系统架构部高级主任测试工程师。他有超过10年的ATE硬件设计经验和SOC/PMIC/RF的调试经验，并在高速信号和射频信号的设计/仿真方面有丰富的项目经验积累。此外，他还拥有8个与ATE硬件相关的专利。