Welcome!
To access the archive contents (presentation slides, videos, multimedia, etc.) sign in using your LinkedIn account by clicking the LinkedIn button to the right. Full Conference Attendees and Subscribers have access to all content now. FREE guests, once signed in, have access to the presentations after June 1, 2013.
------ This message is only displayed when you are not signed in. ------
Session 1 – Streamlining Operations
Test operations, generally considered costly yet necessary, add value to device manufacturing when optimized for efficiency. This session offers a variety of approaches that promise high yields, lean manufacturing, maximized performance at minimal costs, and optimized production times. The first paper discusses a method of incorporating multidimensional Monte Carlo analysis simulation with known design parameters to focus manufacturing improvement efforts and maximize alignment performance while minimizing costs. Presented next is a method for redefining test tooling design rules to gain process margin and prevent substrate chipping caused by test handler misalignment. Zero-cost, software based, virtual tool checkers that bring the whole production area towards a manufacturing LEAN direction is then discussed. Wrapping things up is a paper on a screwless socket and dual pin testing concept said to greatly enhance the robustness and efficiency of IC testing."Improving Socket Alignment Performance Using Monte Carlo Analysis Techniques and Manufacturing Controls"
Daniel DelVecchio, Dustin Allison
Interconnect Devices Incorporated
Presentation Download
"Tooling Stack-up Process Margin Improvement"
Mook Koon Wong, Boon Hor Phee
Intel Malaysia
Presentation Download
"Zero Cost Virtual Tool Checker"
Seong Guan Ooi
Intel Technology Sdn. Bhd.
Presentation Download
"Enablers for Robust & Online Trouble-shooting for High Parallelism Testing"
Benedict Loh
Infineon Technologies
Kohei Hironaka
NHK Springs
Michelle Ng
TestPro
Return to the 2013 BiTS Workshop Archive index page