Semiconductor industry has made great progress in past 20 years. Nowadays the chips are fabricated with billions of transistors and these transistors generate much more heat which cause high heat power dissipation. So chip cooling has become a big challenge for IC Test Industry. In this article, some typical cooling solutions will be introduced, such as metal heatsink cooling, fluid cooling & chiller, heat pipe cooling, etc.
Air Cooling
Heatsinks (HS) always touch IC and press onto socket/PCB to test. For lower power IC test, free air goes through HS tunnels to chill the system. For higher power IC test scenario, HS can’t meet our Temperature request, then it is needed to add an electronic FAN on HS to force cooling the IC Test system.
Water cooling
Heatsinks still can be used in water cooling. Additionally, HS have more tunnels design in its body for water flowing; the tunnels can be made as: series, parallel, pseudo-series, pseudo-parallel. Heat dissipation for HS with water tunnel can overwhelm the air cooling one.
Another method is to add a chiller system to improve the heat dissipation ability for the thermal management proposal.
Heat pipe cooling
HS can be a part of heat pipe cooling system. HS body has several heat pipes inserted upwards. It is the evaporation and condensing of the water that forms a pumping action to move the water (and thus the heat) along the pipe.
Challenge Heat pipe cooling
HS can be a part of heat pipe cooling system. HS body has several heat pipes inserted upwards. It is the evaporation and condensing of the water that forms a pumping action to move the water (and thus the heat) along the pipe
Challenge
The future IC test power will be as high as 1000W or more, then new lid cooling system is a direction of research; Socket cooling ability is still not proficient
Space;
Cost.

Huaqiu “Terence” Miao* is a Mechanical Engineer at Smiths Interconnect Suzhou from 2014. He has over 15-years experiences about mechanical design. Currently his role is designing IC test products and thermal analysis.

在过去的20年里面，半导体工业有了一个长足的发展。如今的芯片包含动辄上十亿的晶体管，如此多的晶体管聚集在一起它们的发热量不容忽视。所以如何给芯片降温就是一个很大的挑战。
本文将介绍几种典型的冷却方法，其中包括金属散热片冷却，水冷和冷却器，热通道管冷却，等等。
*_风冷_*
散热片通常是和芯片直接接触并将芯片压入测试插座或电路板，并最终完成芯片测试。对于低功耗的芯片，空气通过对流通过散热片的鳍片并对系统进行冷却。对于高功耗的芯片，凭借单一的散热片通常达不到控温的要求，这时就需要增加风扇来强制增加风速，从而达到更好的制冷效果。
*_水冷_*
散热片同样也可以用于水冷方式。而且，水冷的散热片设计包含更多的流通通道来保证液体的热量充分交换，这些通道可以设计成，串联，并联，伪串联，伪并联方式。水冷是一种非常高效热交换方式对比风冷的方式。
另外一种方式就是增加制冷器来提高散热的能力，
*_热通道管冷却_*
散热片也可以是热通道冷却系统的一部分。 散热片本体被多个热通道向上接入。正是水的蒸发和冷凝形成了泵送作用，使水（以及热量）沿着管道流动。
*_挑战_*
* 将来的芯片功率可能高达1000W或者以上，所以新的散热方式任然在探索当中……
* 测试插座的散热方式正在捉襟见肘。
* 空间，
* 成本

缪华秋(Terence), 2014年加入史密斯英特康苏州事业部，是一名机械工程师。他有超过15年的机械设计经验。当前他主要从事芯片测试产品的设计和热分析

MEMS Pressure Sensor Testing Solutions and Challenges
Thanks to MEMS (micro-electromechanical systems) technological advances, the applications of automotive electronics, consumer, IOT, mobile device have become more flourishing. MEMS pressure sensors already gained a foothold in market and played an important role in navigation, Quadcopter, environmental monitoring and TPMS… applications. Due to the huge demand for pressure sensors, develop testing and calibration solution to keep abreast of deal with new developments in the MEMS sensor.
This presentation will introduce our achievements of testing calibration systems for MEMS pressure sensor. How to control temperature and pressure will be crucial factors in the MEMS pressure testing, we have to face more challenges of soaking time reduction, chamber temperature uniformity, high pressure chamber design, leakage issues and stable time. The temperature close-loop control and cooling system are used for the purposes of optimal soaking time. In this system, precise temperature control and efficient cooling system become more important. In addition, chamber can fine-tune temperature offset for each area by modular temperature control unit, that temperature uniformity within +/-1⁰C had been achieved. For pressure chamber stability, reliability and leakage, we improved the chamber design to give greater strength and rigidity. Chamber volume is a trade-off between pressure stability and response time for different pressure conditions; Chamber volume problem are simulated, which proves optimization of pressure control time and accuracy.
As previously mentioned, this system has multi chambers for different temperature conditions and also control the heat loss that will make good performance to pressure sensor. For efficient mass production, multi chambers simplify the process of high/low temperature testing, and that reduce the opportunity for operator error.

Cheng-Wen "Hank" Yao currently is Department Deputy Manager of Advance Technology Development Division of King Yuan Electronics Co., Ltd. He has worked for KYEC over six years since he received his Master of Science (M.S.) Electronic Engineering degree from National Ilan University and is responsible for MEMS testing technology development. His experience includes integration of software and hardware systems for MEMS testing solutions for mass production of accelerometers, gyroscopes and pressure sensors, and magnetic sensors.

因微機電製程的進步使得微機電傳感器 (MEMS Sensor)的之應用發展日趨蓬勃，舉凡汽車電子、消費電子、移動裝置、互聯網等都脫離不了其應用範疇。而利用微機電系統技術所製造之壓力傳感器，更已在市場中佔有一席之地，諸如車用導航、四軸飛行器、環境監控、胎壓計等應用都有著密不可分關係，也因此對於製程的進步讓在MEMS測試技術與校正環境的建置開發上則顯得極為重要。
本文將介紹微機電壓力傳感器的測試與校正環境開發與實績，在壓力傳感器測試裡溫度與壓力控制是整體測試關鍵指標，其中挑戰在於腔體機構中影響升降溫時間、均溫性、高壓腔體、漏氣率以及壓力穩定時間等因素設計。
在多腔體機構設計上，首先，溫度控制部份是透過溫度回授感測與散熱系統來縮短升降溫的時間，而精準溫控變化與散熱效率將為關鍵；設計中對腔體的均溫性採用控溫模組來進行各區域微調以達+/- 1℃內；再則，壓力測試部分則強化腔體機構設計增強壓控穩定度與可靠度，減少漏氣產生，透過模擬腔體容積優化實驗，取捨於壓力穩定與反應速度上，讓壓力精準度與測試時間成本達到最佳化。
以上設計乃將大幅提升傳感器的效能，透過模擬溫度傳導減少散失與機台上多腔體變化排列，簡化了各腔體升降溫流程減少人為造成之異常，提升整體生產效率。

姚承汶目前服务于, 京元电子尖端测试技术开发处 . 承汶在京元电子工作已超过6年, 自從研究所畢業獲得硕士学位. 他目前擔任MEMS产品测试技术整合部门副经理 ,主要負責MEMS产品的CP/FT测试程式开发及 MEMS测试解決專案的系统軟硬體整合。在测试 MEMS加速度计、陀螺儀、壓力计与磁力计..等, 有很豐富的量产经验. 硕士 / 电子工程学系 / 国立宜蘭大学 .

The traditional method of Highly Accelerated Stress Test (HAST) or Temperature Humidity Bias (THB) is to stress the devices at high voltage, high temperature and high humidity chamber. Devices are then powered down and cooled back to room temperature at intermediary predetermined stress time to be tested at ambient conditions by an external electrical test system. Once the electrical characterization is completed, the devices are put back to the chamber and powered back again to the stress voltage at HAST or THB conditions for the next cycle of stressing.
This qualification process ensures the devices tested are not affected by degraded DUT boards, sockets, interconnects and cable assemblies inside the HAST chamber. This process is not only time consuming, but more importantly, are extremely laborious and lack missing real-time electrical test results on the functionality and performance of the devices during stress.
There are more devices requiring low-level leakage current measurements and high voltage stress. To date, there are no known DUT boards, sockets, interconnects and cable assemblies that can work in HAST or THB chambers that are capable of high isolation. This is especially so for electrical measurement requiring pico-Ampere leakage current under high temperature and humidity conditions. As such, no electrical measurements or characterizations can be done in-situ during the HAST and THB. This further means that there is no immediate accessibility of precision electrical data throughout the stress cycle.
In this presentation, we put up a qualified set of DUT Boards, sockets and cable assemblies that are fully capable to work under high temperature and high humidity conditions, and yet still able to provide low leakage electrical measurements with leakage down to 10pA/V level. Each of these parts are independently qualified and put together as a burn-in interface under HAST and THB without much degradation and thus will not impact the actual in-situ test of DUTs during stress.
In this presentation, we will also show the results in-situ electrical measurements throughout HAST and THB, even down to pico-ampere level measurements. The DUT interfaces are designed and developed with proven data to be able to provide low leakage electrical characterization, and continuous electrical monitoring capability under high temperature and humidity.
With this system and setup, users would not only be able to have the electrical data to understand the changes of the devices throughout the qualification process, but also save the time and uncertainties induced on the devices after powered down and transferring of the devices to another system for electrical measurement after each stress cycle.

Yi-Ming Lau is the Senior Director of the R&D Department of STAr Technologies. She joined STAr in 2005, and has since served as the Product Manager for STAr Reliability Test Systems. She is responsible for the development and integration of advanced reliability test solutions, as well as applications and sales support for reliability systems. She holds a Masters of Engineering & Bachelor of Engineering in Electrical Engineering from National University of Singapore, and a Diploma in Law with a Mark of Credit from University of London (External). Prior to joining STAr, she worked as a Senior Failure Analysis Engineer with Micron Semiconductor Asia, responsible for device level failure analysis.

皮安级别的现场电气加速寿命试验
传统的HAST（加速寿命试验）或者THB(加速式温湿度及偏压测试)都是用高压，高温度和高湿度腔体的情况下完成加速测试。然后，通过外部电气测试系统在相关的环境温度中根据中间预定应力时间，关闭设备电源并冷却至室温。一旦电气特性测试完成后，这些芯片将被放回试验腔体里面，在HAST或THB条件下再次通电至加速电压，以进行下一个应力循环。
该认证过程确保被测芯片性能不受HAST试验腔体里DUT板、插座、互连和电缆组件的弱化影响。这一工艺不仅耗时，而且更重要的是，非常费力，而且在加速测试条件下缺少设备功能和性能的实时电气测试结果。
越来越多的芯片需要低水平的漏电流测量和高电压加速测试。到目前为止，还没有已知的DUT板、插座、互连和电缆组件可以在HAST或THB室中表现出高隔离度的性能。特别是在高温和潮湿条件下需要皮安级别漏电流的测量。因此，在HAST和THB期间，很难在现场进行任何电气或表征化测量。这进一步意味着在整个加速实验周期内，无法直接获取精确的电气数据。
本文介绍了一套合格的DUT板、插座和电缆组件，它们完全能够在高温和高湿度条件下工作，并能够提供低泄漏的电测量，漏电流水平低至10pa/v。每一个部件都是独立合格的，并在HAST和THB下作为老化接口组装在一起，不会有太大的性能弱化，因此不会在加速实验期间影响DUT的实际测试效果。本文还将展示整个HAST和THB的现场电气测量结果，甚至可以达到皮安级别。DUT接口的设计和开发经过大量的数据验证，能够提供低漏电流的特性，以及在高温和湿度下的连续电气监测能力。
有了这个系统，用户不仅能够获得电气数据来了解整个认证过程中芯片的变化，同时也节省了每一个加速实验周期结束后，将设备断电并转移到另一个系统进行电气测量所产生的时间和不确定性。

劉毅敏是一位資深處長, 服務於思達科技股份有限公司之研究開發部門. 她於2005年加入思達科技, 從思達的半導體可靠度測試系統的產品經理開始做起. 她負責高階半導體可靠度測試系統解決方案的開發與整合, 也同時負責系統可靠度測試的應用及業務端的支援. 她擁有新加坡國立大學電子工程之碩士學位, 以及倫敦大學法學专科學歷. 在進入思達以前, 她任職於美光半導體資深故障分析工程師, 負責半導體器件故障分析.

Several technology market trends are driving semiconductors to more stringent reliability requirements. The continued pervasion of electronics in automotive due to electrification, connectivity and autonomous driving is increasing dramatically the number of ICs in each car. This is coupled with an increase in chip complexity and pressure to shorter time-to-market cycles. Also, as is well known, Integrated Circuits reliability follow the bathtub curve. In its central region, the bathtub curve has the lowest, approximately constant, failure rate. Failures occurring in this region are defined “random” and are not detected by the traditional test flow (Final Test + Qualification & EFR test). As shown in literature, the majority of these, called “intermittent failures”, may be activated and deactivated by voltage, frequency, and operating temperature variations, in other words by stress conditions. The existing IC qualification flow and testing flow during manufacturing are no longer adequate to meet the higher functional safety or mission critical requirements. Even a 1ppm failure rate is too high. Not detecting random and intermittent failures, for such applications the traditional reliability flow and traditional test flow are therefore not suitable, obliging to adopt mitigation strategies such as redundancy. This paper describes a holostic reliability test approach called RETE (Reliability Embedded Test Engineering), which encompasses aspects from both AEC-Q100 and AEC-Q004. It starts with DfRT (Design for Reliability Test) at Design stage, a strategy for TFR (Test for Reliability) implementation, and data analysis to support a Learn-from-Fail feedback cycle. Practical applications of RETE to different semiconductor segments are described, supporting the road to zero defects.

Nigel graduated from London's UCL in Electronics Engineering & Computer Science in 1985, followed by postgraduate research in Semiconductor Reliability. He worked for STMicroelectronics in Malta in Test Engineering functions including Technical Director, and as Corporate Testing Director for worldwide manufacturing based in Singapore. He occupied the position of President & General Manager of ON Semiconductor for their two manufacturing plants in Philippines, and is currently responsible for Strategic Business Development at ELES Semiconductor Equipment, Italy.

市场的趋势要求半导体芯片具有更高的可靠性，汽车自动驾驶及其他电子功能大大增加了汽车里半导体芯片。同时，芯片的复杂程度亦增加，又要减少芯片研发至投入市场的时间。集成电路的可靠性类似浴盆形成，中央区是最低且平，相当于稳定的失效率。在该区的失效可定义为“随机”。传统的方法很难测定。众多文献上描述为“间歇式失效”，可能由电压的开闭和效率及温度有关，或称之为“应力条件”。现有的测试方法不再满足功能安全的要求，1PPM的失效率都太高。
本文要介绍“Holostic”可靠性测试，称之为RETE（Reliability Embedded Test Engineering）.它综合AEC-Q100和AEC-Q004,它从设计阶段开始采用DFRT（Design for Reliability Test）和TFR战略（Test for Reliability）及数据分析来支撑Learn-from-Failure循环。此方法在半导体产品的实例将在演讲中介绍。

Nigel G Kissaun 1985年毕业于伦敦的UCL 电子工程和计算机系并从事半导体可靠性研究（postgraduate). 在STMicro (Malta) 从事多项测试工程相关职务，包括技术总监，全球芯片制造测试总监(新加坡). 他曾担任On Semi在菲律宾二????制造工厂的总裁和总经理. 目前担任在意大利的ELES Semi Equipment 的商业发展总监。

Limited quantity of first article silicon and customer reference board (CRB) to support silicon debug or test is a challenge in semiconductor industry today. Semiconductor manufacturer did not produce huge quantity of first article silicon due to technology instability and involved huge manufacturing cost. The situation become more challenging when the manufacturer extended the debug/test coverage to their customer, example shipping limited silicon to their customer who resides in different geographical location which may caused up to weeks of delay and impact the overall time-to-market (TTM).
Current Technology Limitation:
Some 3rd party remote access software like TeamViewer & VNC were used by the manufacturer to establish a virtual debug environment with their customer to address the silicon/CRB limitation issue. Typically, these connections are done thru a non-secure internet connection and may lead to Intellectual Property (IP) leak.
Solution:
Intel has come out with a breakthrough solution by introducing a cloud based remote debug (CBRD) infrastructure which allow external customer to have first-hand access to first article silicon debug. The entire CBRD concept is to establish an end to end debug experience to all the user, which covers connectivity, CRB configuration/setup/booking system, remote debug experience and automated testing capabilities. This solution consists of 2 major architectures: Secure Access & Board Farm. CBRD applied 4 layers of Multi Factor Authentication (MFA) for secure access. Each user will need to register in Intel database to obtain an online certificate & login credential to establish a secure VPN tunnel to Intel’s environment. Board Farm architecture consists of asset management system, platform scheduling system with auto OS provisioning and extensive remote debug features such as remote power cycling for a platform, remote DC & RF signal probing & BIOS post screen access & debug. Individual debug environment can be create by the administrator on the fly. CBRD operates in 24x7 and allow user to perform debug activities remotely, anytime and anywhere. With this solution in placed, early bugs or sightings can discovered and Intel can response to the fix in a much more early stage to reduce the number of silicon design stage – a new agile way for silicon debug process.
Conclusion & Implementation:
This solution is able to improve the silicon debug process by weeks, reduced the total numbers of CRB and first article silicon produced per project (>50% hardware cost savings), improve the lab operation to 24x7 (improve utilization) and accelerate the time to market for a new product release. Intel has received a huge demand from customer to extend this capability across the globe.

SG Ooi holds a bachelor’s Degree in Electronics Engineering. SG starts his career with Teradyne Inc. as Field Application Engineer before joined Intel. SG hold several technical positions throughout his career in Intel and his current position is the staff technologist and product owner for global post-silicon. SG expertise are in mix signal device debugging and end to end system design. SG is a certified SAFe Agilist and also an active technical paper author with more than 20 technical papers published for internal and external technical conferences. SG also hold a patent in Smart Sensor solution for IoT.

See Tien "Angie" Ng graduated with Master in Engineering (major in microelectronics) from Multimedia University Malaysia. She currently pursue a part time doctorate study with University Science Malaysia. Angie is Technical Lead for Intel Malaysia Internet of Things Group, a certified FUSA Automotive Engineer and also comes with 22 years industrial working experience.

**云数据进行远程调试**
主题词： 模块和芯片测试挑战—测试自动化
少量的首批芯片样品和测试用户参考线路板是半导体测试行业中进行芯片测试调试时的一个挑战，芯片制造厂由于工艺的不稳定和制造成本而不顾意提供很大数量的首样，由于担心测试调试成本的增加和影响产品上市时间， 这个挑战变的更大。 芯片制造厂可以利用第三方的远程切入软件，如TeamViewer 和VNC 进行模拟调试环境和其客户共同解决首样数量不足和参考线路板的问题。由于数据传输通过非安全的外部网络，从而担心知识产权的保护问题。
解决方案：英特尔采用了云基远程调试(cloud based remote debug， CBRD)的突破性技术。客户可以直接切入进行首件芯片调试。这个系统的基本概念是所有的调试经验可以提供给使用者，它包括了连接性，参考线路板架构/设定和远程调试经验和自动测试的能力，此解决方案由二个主要架构组成： 安全切入和板植入(Secure Access & Board Farm)。CBRD 有四层多因子验证确保安全性。每一个用户需要在英特尔的数据库上注册取得授权去建立一个安全的VPN通道进入英特尔数据库，板植入架构则由下列分支组成：资产管理，平台计划系统可自动OS分部或广泛的远程调试和功率循环，远程DC 和RF信号测定和BIOS 适屏调试。个别用户调试环境由管理户远程建立。CBRD是7天24小时运行，用户可任何地点任何时候进行远程调试，此系统的使用， 有助于芯片的研发早期的调试和问题的解决，从而减少了芯片调试的时间和成本。
CBRD系统的实际应用使芯片研发调试时间缩短数周，芯片首样和参考线路板数量减少 (50% 以上成本降低) ，改善了实验室操作成为24x7 (充分使用) ，加速了新产品开发和上市的时间，英特尔已经全球众多产品要求去拓展此系统的能力。

SG 拥有电子工程学位。加入Intel前在Teradyne Inc 任客户服务工程师。在Intel 担任过不同的技术职务，目前担任全球“post-silicon”资深技术专家和产品负责人。SG专长是复合信号芯片的故障分析排除和终端间的系统设计。SG 是注册SAFe Aglist并在内部和外部的技术会议上发表20余篇技术文章。拥有一个用于IoT的智能感应会的专利。

Angie毕业于馬来西亚的Multimedia University, 微电子专业硕士。目前在University Science Malaysia 攻读博士学位。Angie 是Intel Malaysia IoT 部门的技术领导，拥有FUSA注册工程师, 和22年企业工作经验。

IC test engineer like to using inductance and capacitance for socket model to debug and run analysis for their circuitry. This is simple way to evaluate the socket performance base on the extracted value of lump RLC. And most of the time the inductance plays more important role compare with capacitance.
In this paper, we report a basic study on various ways to extract the inductance of a socket model, and discuss the difference across varies math models.
Next by study a Saw filter application case, we discuss how correlation of these models compare to embedded s-parameter. We proposed several designs base on the embedded s-parameter math model to improve the socket. The experimental results confirmed the simulation data and proven embedded s-parameter is more correlated the real test result, and provide better prediction of socket design change.

Yoinjun Shi is currently CTO of Twinsolution Technology Shanghai Inc., He has Bachelor Degree of electronic engineering from Suzhou University and MBA from Victoria University Switzerland. Yoinjun has over 15 years’ experience in the semiconductor industry. Now Yoinjun’s major focus is on developing high quality metal contactors. He is a member of the BiTS China Technical Program Committee.

集成电路测试工程通常喜欢使用测试插座的电感和电容去调试和分析他们的电路，以及最后的测试效果。这是一个非常简单的方法来评估测试插座的效果根据提取的寄生电感电容参数。很多时候电感会起比较大的作用。
本文讨论几种不同的提取测试插座电感的方法，并讨论了他们的差异。
最后通过一个滤波器的测试插座案例，我们分析讨论的嵌入式S参数的方法和其他方法的差别。根据嵌入S参数的方法，我们讨论了不同的测试插座的设计并对比实际测试效果。实验结果验证和检验了嵌入S参数的方法比较接近实际测试结果，并能对测试插座的设计提供指导参照。

Yoinjun Shi 施 元军目前是上 海韬盛电子科技股份有限公司的研发经理。他在半导体测试产业有超过15年 的经验，并致力于测试连接器对信号和电源完整性影响研究多年， 他还多次提交并获得专利。其中以高 隔离度的测试插座的研发最具代表性。现在他主要专注于开发低接触电阻和长寿命的金属接触探针。