The ideal transparent socket would make us millions if we could actually find it, but in the real world we cannot simply time travel between two points and ignore what is in the middle. At DC the focus is on the contact resistance, but at the high frequencies of multi-gigabit interconnects one can be plagued by additional dielectric loss, reflections, and complicated multi-mode resonances. This means that if your socket is not working as required at 8, 16, 28 or 40 Gbps then that classic voltmeter sitting on the test bench is not going to do the job. Signal Integrity expert, Dr. Eric Bogatin, emphasizes that a good engineering practice is to always have models or simulations to predict the outcome of a measurement. Often there is a large void between the too simple V=IR calculation and the too complicated full 3D-EM simulation with Maxwell’s equations. Engineers confronted with these two options will typically do nothing on the simulation side and then just point to the data sheet.

A better option is to explore the power of simple transmission line theory and network analysis with scattering parameters (S-Parameters). Simple deconstructed transmission line models can be used in simulations to quickly evaluate the impact of resistance, dielectric loss, reflections, and even resonances. The results of the simulations provide valuable insights into how transparent a socket is for your application. Using hands-on computer labs with both frequency domain and time domain simulations attendees at the workshop will be able to test out their ability to debug a failed test socket measurement and get a socket design that is transparent for an 8.4 Gbps PCIe application example. These simple deconstructed transmission line models also improve the effectiveness of full 3D-EM simulations. Knowing what to expect from the EM simulation insures better setup of the stimulus ports, and effective use of simplification trade-offs.

Another way to make a transparent socket is to mathematically remove its effects from the measurement. This can be a simple calibration of removing a static IR drop at DC, but at high frequencies one must calibrate out both the “attenuation” drop and the interaction of reflected signals. To make things even more complicated, one must also keep track of the phase relationship between the current and voltages at high frequencies. Simple transmission line theory and network analysis scattering parameters (S-parameters) do just that, and with a bit of matrix math they can remove the effects of the socket fixture from a measurement. The signal integrity world calls this fixture de-embedding. Using hands-on computer labs and actual test equipment hardware attendees will learn how to measure socket fixture S-parameters using a two-tier Short/Open/Load/Through (SOLT) with 2-port probing or 1-port open calibration techniques. The socket fixture S-parameters can then be used in the time domain to remove the effects of the socket fixture from the measurement making the socket transparent. This sounds too good to be true, and so again one can turn to simulation to see where it can go wrong and get a practical understanding of how and when to implement fixture de-embedding.

The goal of this half-day tutorial is to give the attendees a toolbox of both simulation and measurement signal integrity techniques for characterizing a socket and ways to make it transparent for high frequency multi-gigabit applications.

Note: Due to the hands-on nature of this Tutorial, attendance will be limited. Please sign-up early to not miss out!

Mr. Prior will share an overview of the global packaging market. His presentation will focus on the impact and growth of small form factor packages such as multi-row QFN, WLCSP, Fan-Out WLCSP and MIS BGA on the electronics industry infrastructure. Teardowns of products from early adopters such as Apple, Samsung, Huawei, and Xiaomi will be used to highlight how fast this change is occurring.

Welcoming remarks from the General Chair, Ira Feldman

Mr. Joe Bruen will share his thoughts on microelectromechanical systems (MEMS) sensing technology and the end applications which include automobiles to smartphones and everything in between. He will explore the Internet of Things (IoT) which will connect all these devices and will become the Internet of Tomorrow.

With microelectromechanical systems (MEMS) devices in consumer products becoming as common as parades on St. Patrick’s Day, reducing the cost of test is more important than ever. It is no wonder the MEMS test session addresses lowering the cost of MEMS test. John Rychik, Xcerra, describes various approaches to reduce the cost of calibration and test through test cell integration. Vesa Hentonnen, Afore, covers three ways to decrease the cost of test to less than one cent. These are parallelism, shortening the process, and choice of tester. Wendy Chen, KYEC, explains a cost effective test strategy achieved by adding built-in-self test (BIST) and built-in self-calibration (BISC). These design-for-test methods can be applied to MEMS devices by integrating a single CMOS die or through 3D stacked die integration. The session closes with Peter Jones, Freescale, discussing a novel method for performing stress tests on MEMS die-form pressure sensors.

Test socket solutions and the requirements of the device under test (DUT) vary according to the device end application. This session spans the socket spectrum from automotive applications, which require devices to withstand extreme temperature and high current, to mobile applications, which have high cost sensitivity. Markus Wagner, Cohu, explores contacting solutions for high power bare die testing. Valts Treibergs, Xcerra, compares different methods for determining current carrying capacity in test socket interconnects. Andreas Nagy, Xcerra, gives an overview of test temperature requirements of automotive and consumer applications and discusses consequences for test strategies. Praveen kumar Ramamoorthy, Infineon, focuses on socket design and development specifically for the extreme temperature and high current testing challenges of automotive devices.

Poster Sessions are a great way to network through interaction with the poster presenters and other curious bystanders. At the same time enjoy the break refreshments and networking.

Wafer level chip scale packages (WLCSP) are all the rage, and testing them is becoming easier and more cost effective as new probe technologies and probe card designs become available. This session explores four newly developed test solutions for WLCSP. Frank Zhou, Smiths Connectors, presents a tip co-planarity analysis of a 200 µm pitch spring probe head for WLCSP. Zhou describes the structure of the probe head and spring contact probes along with key features and their impacts on co-planarity of probe head contactor tips. Paul Gunn, Test Tooling Solutions Group, reports on design for manufacturing (DFM) efforts in the development of a 0.2mm WLCSP test socket. Khaled Elmadbouly, Smiths Connectors, discusses the challenges of building fan-out printed circuit boards (PCB) for use as space transformers in probe heads for multi-site WLCSP with pitches greater than 0.2 mm.

The BiTS EXPO is a very popular part of the BiTS program with many great exhibits to explore what is Now & Next in the test and burn-in of packaged semiconductors. There is always something new to see or someone new to meet. Not to mention excellent food, drinks, and time for attendees to network with exhibitors!

Contacts, test probes, and sockets have to accommodate ever-finer pitches, while holding up repeatedly to increasingly stressful conditions. This session looks at the impact of choosing the right materials and fabrication processes to address these situations and to increase the life of test consumables. Mike Gideon, Materion, discusses reliability and failure over time along with how to prevent failure by understanding root causes. Jimmy Johnson, Tyco Electronics, investigates using cold heading technology, selective gold plating, and a proprietary plating process to produce lower cost, high-reliability burn-in and test sockets. Jeb Flemming, 3D Glass Solutions, explores glass as an alternative to injected molded plastic for cost-effective test and burn-in sockets for radio-frequency (RF) device test. Bert Brost, Xcerra, talks about a novel coating technology that prevents solder migration at the contactor tips, thereby improving contact stability.

Test cell integration is best not left to the “luck o’ the Irish.” Testing today’s packaged semiconductor devices requires careful integration of automated test equipment (ATE) and handlers to reduce the cost of test. In this first of two sessions, presenters examine ways to streamline processes as well as alternative approaches that reduce the need for costly ATE and handlers. Alexander Wieler, esmo, starts with a semi-automated device interface board (DIB) loader, which allows for the quick exchange of DIBs without undocking the tester from the handler. Raimondo Sessego, Freescale, introduces a novel approach to testing MEMS G Cell devices. Stanley explains how this mechanical-flip burn-in system for tire pressure monitoring system (TPMS) sensors eliminates the need for a high cost ATE and flip handler combination. Mike Frazier, Xcerra, reviews the challenges of testing and handling singulated WLCSP devices using a strip or carrier format.

Simulation and modeling of performance is one of the most crucial design tasks for developing test hardware. It is essential to ensure the highest possible performance from wafer probes, sockets, contactors, and printed circuit boards. Mohammed Eldessouki, SV Probe, details the importance of implementing electrical performance simulation of the probe head on a semiconductor wafer probe card using SPICE based simulators. Gert Hohenwarter, GateWave Northern, reviews characterization and use of Kelvin sockets at RF frequencies. He explains that the proper design and analysis of the test environment requires knowledge of the input and output parameters of the DUT. Don Thompson, R&D Altanova, discusses measuring a socket at very high frequencies and the rational for this methodology. Jose Moreira, Advantest, reviews a 32 Gbps application that presents challenges for PCB test fixture and socket design. Jose describes the ATE system measurements results and improvements required.

Continue to explore the great exhibits at the BiTS EXPO to see what is Now & Next in the test and burn-in of packaged semiconductors. There is always something new to see or someone new to meet. Refreshments and drinks are served but don't spoil your appetitute before the BiTS Social...

Don't miss the BiTS celebration of St. Patrick's Day! There will be plenty of excellent food and drink inspired by the holiday with a twist. And you'll get to try your luck in the BiTS Casino!

In this second test cell integration session, we hear specialized test solutions that target very specific requirements. Jason Mroczkowski, Xcerra, describes a complete test cell for high volume manufacturing (HVM) that meets the challenges of RF testing for next generation automotive radar devices. Bob Bartlett, Advantest, describes a universal device interface (UDI) framework that can be used by test engineers to quickly integrate any kind of PCB evaluation board or device interface for characterization, bring-up, and HVM. Roger Sinsheimer, Teradyne, explains how to extend existing ATE test instruments in new ways for specialized test requirements for niche markets solutions.

It's been three and a half days packed with learning, exploring, and sharing. Before we pack our bags and take what we've learned back to our jobs, there are a few closing remarks. We will take a moment to reflect and recognize the people, presentations, and posters that have distinguished themselves at BiTS 2015.