In this tutorial, we will go over the socket contact element fundamentals, types of socket contact elements, contact element materials, and printed circuit board (PCB) & hardware requirements. We will also cover electrical, and system design and test requirements. We will provide you with different options for selecting interconnect sockets depending on your requirements like signal integrity, cycle life, cost, etc.

At the end of the course, you will have a clear understanding of the types of sockets available in the industry, how to select the best one for your needs, and how to successfully develop and implement the same.

Target audience includes: PCB designers, mechanical engineers, hardware engineers, hardware engineering managers, and materials engineers.

Objectives

• Understand what the interconnect socket is and its benefits
• Understand the contact elements and resistances
• Understand different types of interconnect sockets available in the industry and their applications
• Provide overview of different PCB plating available in the industry and their applications
• Understand mechanical system design methodologies with special emphasis on tolerances, PCB Keep-Out-Zones (KOZs) and retention design
• Provide overview of electrical signal integrity measurements
• Understand test and validation requirements for interconnect technologies
• Understand the entire end-to-end process flow, right from gathering the requirements to successful implementation

Note: Attendance at the tutorial will be limited. Please sign-up early to not miss out!

If this is your eighteenth time attending BiTS Workshop, only your first, or somewhere in-between you will feel welcomed at the opening reception by friends old and new.

The first of many excellent meals awaits as you get to network with other industry professionals. This is a great time to catch up with old colleagues or start meeting new friends.

The eagerly awaited overviews of the socket and contactor market along with general market trends will set the stage for what is now & next in test.

Start the day right and enjoy the continental breakfast while networking with other attendees.

Welcoming remarks from the General Chair, Ira Feldman

Supply chain complexity is driving the need for new and increasingly advanced analytical solutions to ensure products are delivered on time and with the highest possible quality. In the future, it will become essential for companies to produce digital threads linking all relevant information into product signatures. These product signatures can then be diagnosed and translated into actionable intelligence throughout the value chain. However, to realize this end-state, companies will need to embrace a new paradigm of trust and collaboration.

The industry’s challenge is to create this type of enhanced traceability without sacrificing the intellectual property (IP) and security of product (IP) companies, manufacturers and suppliers. This is further complicated by the level of maturity and information technology (IT) sophistication of the various stakeholders within the electronics ecosystem. By leveraging the Internet of Things (IOT) and associated technologies, companies can quickly integrate advanced analytical and control solutions into their manufacturing environments, accelerating the adoption and the resulting benefits of the analytics.

With the shared goal of establishing real-time situational awareness for improved value chain decision-making, companies will embrace this next stage of industry evolution – the migration to a connected digital environment that enables a flexible, adaptable and intelligent product delivery system. The resulting return on investment (ROI) from this type of investment will continue the industry’s long term trend of delivering the right products, at the right time and with the requisite economics to ensure both consumer and commercial adoption.

Enjoy the break and networking time.

Always connected mobile devices – from smartphones to automobiles - are driving the need for higher performance test solutions as bandwidth and frequency requirements increase. Markus Wagner of Cohu and Milen Cheshmedjiev of Melexis discusses development and characterization of a new contact technology focused on achieving high current and stable contact resistance required for long-life tri-temperature automotive applications. Next generation 5G communication will use millimeter (mm)-wave frequencies and Carol McCuen of R&D Altanova shows how to improve the performance of the printed circuit board (PCB) in these higher frequencies. Noureen Sajid of Johnstech International reviews testing of 80 GHz QFN packages demanded by automotive radar, telecommunications, and other new millimeter-wave applications. Contactor-based testing of automotive radar presents significant challenges highlighted by Brian Nakai of NXP Semiconductors.

Lunch is served. Enjoy the break and networking time.

As test application challenges continue to increase, old “rules of thumb” are no longer good enough for design. Electrical simulation is essential to knowing if a solution will work before it is built. Frank Zhou of Smiths Connectors discusses simulation and measurement results showing how impedance controlled sockets have evolved over time to handle higher frequency requirements. Designing and verifying next generation transceivers running at 100 Gbs pose significant challenges presented by Jackie Luo of Zenfocus Semi-Tech. As frequencies rise, every detail including the metal used in the pad “stack” matters as Gert Hohenwarter from Gatewave Northern demonstrates. Yuanjun Shi of TwinSolution Technology provides results from finite element analysis (FEA) and lab measurements to support very high current applications.

Poster Sessions are a great way to network through interaction with the poster presenters and other curious bystanders. At the same time enjoy the break refeshments and networking.

Everything can be designed “properly” and be within specification and still not work as intended. There are many challenges and new product “bring up” doesn’t end until the design is fully validated. Testing devices in the product environment pose their own special challenges. Instead of developing special validation load boards, John Kelbert of Intel shows using an interposer approach to add the required capabilities to the product PCB. Matthew Priolo of Intel reviews challenges and solutions for cases where the validation test hardware requires more space than is available on the product PCB. Not only do products require careful validation, so do production device under test (DUT) setups as Martin Gao from Texas Instruments explains.

The BiTS EXPO is a very popular part of the BiTS program with many great exhibits to explore what is Now & Next in the test and burn-in of packaged semiconductors. There is always something new to see or someone new to meet. Not to mention excellent food, drinks, and time for attendees to network with exhibitors!

Start the day right and enjoy the continental breakfast while networking with other attendees.

Designers of printed circuit boards (PCBs) for use as test load boards and burn-in boards face many challenges driven by the test and operational requirements. Willy Ganoy from ON Semiconductor reviews a new design method to permit switching of contact technology on the load board. How to burn-in high frequency low voltage differential signal (LVDS) devices is a challenge that Rolando Reyes of Analog Devices explores. Bruce Mahler demonstrates new ways of embedding thin film heaters for precise DUT temperature control. Developing retrofitting legacy burn-in boards to handle voltage surges is more practical than replacing them as shown by Gil Conanan of Analog Devices.

Enjoy the break and networking time.

Measuring device under test (DUT) performance under different thermal conditions is an essential part of a robust test process. Accurate characterization and control of the heat is necessary for accuracy, repeatability, and avoiding device damage. Standardization and auditing is essential to improve burn-in yield and quality as shown by Jeanette Linn from Texas Instruments. Barry Johnson of inTEST Thermal discusses options for managing and forcing DUT temperatures at the load board and system board levels. It is important to have a process to qualify the high voltage stress applied during burn-in explains Krishna Mohan Chavali from Globalfoundries.

Similar to thermal testing, MEMS testing requires a variety of non-electrical stimuli which present their own challenges. Wendy Chen of KYEC reviews the challenges of MEMS device testing in a very complex supply chain.

Lunch is served. Enjoy the break and networking time.

There are many challenges to making good electrical contact including high current, fine pitch, and other application specific requirements. Thiha Shwe of Texas Instruments high current problems solved. Challenges of a new board-to-board application are explained by Derek Biggs from Plastronics. Valts Triebergs of Xcerra Corporation summarizes new and existing industry approaches to 0.2 mm pitch wafer level chip scale packaging (WLCSP) contact. A standardized approach for managing burn-in sockets is discussed by James Tong from Texas Instruments.

Continue to explore the great exhibits at the BiTS EXPO to see what is Now & Next in the test and burn-in of packaged semiconductors. There is always something new to see or someone new to meet. Refreshments and drinks are served but don't spoil your appetitute before the BiTS Social...

To be Announced...

Start the day right and enjoy the continental breakfast while networking with other attendees.

As test requirements in performance and cost become greater challenges, higher levels of integration are essential in the test cell. Any single element – material handling, test electronics, consumables including load boards and contactors, software, etc. – that is poorly integrated or fails can cause the entire test cell to fail. Finite element analysis (FEA) can be used to predict performance of interface hardware explains Jason Koh of Test Tooling Solutions Group. Yaniv Raz from Intel demonstrates how they automated the physical handling of burn-in boards which have become significantly heavier as additional test functionality is added. The challenges of test and burn-in for optical devices in package and on-wafer is shown by Carl Kasinksi of Aehr. Mike Frazier of Xcerra presents how to handle and test singulated wafer level chip scale packaging (WLCSP).

Enjoy the break and networking time.

There were an abundance of excellent presentations on the challenges of contact technology, so a second session was needed to focus on high frequency applications. Gerhard Gschwendtberger of Cohu explains a new type of contact element for very small contacts for high frequency and analog applications. Additional improvements in their hybrid micro-electromechanical system (MEMS) and elastomer technology is shared by BoHyun Kim from TSE. Jason Mroczkowski of Xcerra reviews and compares flat and radial probe technologies for high frequency testing.

It's been three and a half days packed with learning, exploring, and sharing. Before we pack our bags and take what we've learned back to our jobs, there are a few closing remarks. We will take a moment to reflect and recognize the people, presentations, and posters that have distinguished themselves at BiTS 2017.

Program subject to change without notice.